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參數(shù)資料
| 型號： | ISPLSI2064VL-165LT100 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | EE PLD, 8 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 188K |
| 代理商： | ISPLSI2064VL-165LT100 |
5
Specifications
ispLSI 2064VL
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-135
MIN.
—
—
135
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030/2064VL
1
3
2
1
( )
-100
MIN.
—
—
100
MAX.
7.5
10.0
MAX.
10.0
13.0
DESCRIPTION
#
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
ns
ns
MHz
—
—
—
—
—
A
—
4
5
6
7
8
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
—
—
—
4.5
—
—
—
—
5.0
MHz
MHz
ns
ns
ns
—
0.0
—
0.0
—
—
A
—
A
—
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay, ORP Bypass
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
6.0
—
0.0
—
5.5
—
—
—
—
—
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
—
0.0
—
—
6.5
—
—
—
—
—
—
—
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
3.5
3.5
—
—
—
—
ns
ns
95
143
5.0
—
5.5
—
8.0
—
12.0
12.0
7.0
7.0
77
100
6.5
8.0
5.0
5.0
13.5
15.0
15.0
9.0
9.0
-165
MIN. MAX.
—
—
165
5.5
8.0
—
—
—
—
4.0
—
—
0.0
4.5
—
0.0
—
5.0
—
—
—
—
3.0
3.0
—
—
118
166
3.5
—
5.0
—
6.0
—
10.0
10.0
6.0
6.0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI2064VL-165LT44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000B RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096-100LQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2096-100LT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| ISPLSI-2096-125LQ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI2096-125LQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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