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參數(shù)資料
| 型號： | ISPLSI2064VE-135LT44I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, TQFP-44 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 200K |
| 代理商： | ISPLSI2064VE-135LT44I |
10
Specifications
ispLSI 2064VE
32-I/O Signal Descriptions
GOE 0/IN 3
This pin performs one of two functions. It can be programmed to function as a Global Output Enable
pin or a Dedicated Input pin.
This pin performs one of two functions. It can be programmed to function as a GLobal Output Enable or
a Dedicated Clock input. This clock input is connected to one of the clock inputs of all GLBs on the
device.
This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock
Deistribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active
Low (0) Reset pin which resets all of the registers in the device.
Input
–
Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State
Machine. When
BSCAN
is high, it functions as a dedicated input pin.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as a pin to control the
operation of the ISP State Machine. When
BSCAN
is high, it functions as a dedicated input pin.
Output/Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as an output pin
pin to read serial shift register data. When
BSCAN
is high, it functions as a dedicated input pin.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as a clock pin for the
Serial Shift Register. When
BSCAN
is high, it functions as a dedicated clock input. This clock input is
brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on
the device.
Ground (GND)
Vcc
No Connect
Input/Output pins
–
These are the general purpose I/O pins used by the logic array.
GOE 1/Y0
RESET
/Y1
BSCAN
TDI/IN 0
TMS/IN 2
TDO/IN 1
TCK/Y2
GND
VCC
NC
1
I/O
64-I/O Signal Descriptions
RESET
GOE 0, GOE1
Y0, Y1, Y2
Active Low (0) Reset pin resets all the registers in the device.
Global Output Enable input pins.
Dedicated Clock Input
–
These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
Input
–
Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State
Machine. When
BSCAN
is high, it functions as a dedicated input pin.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as a clock pin for the
Boundary Scan state machine. When
BSCAN
is high, it functions as a dedicated input pin.
Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as a mode control pin for
the Boundary Scan state machine. When
BSCAN
is high, it functions as a dedicated input pin.
Output/Input
–
This pin performs two functions. When
BSCAN
is logic low, it functions as an output pin
to read serial shift register data. When
BSCAN
is high, it functions as a dedicated input pin.
Ground (GND)
Vcc
No Connect
Input/Output Pins
–
These are the general purpose I/O pins used by the logic array.
1. NC pins are not to be connected to any active signals, VCC or GND.
BSCAN
TDI/IN 0
TCK/IN 3
TMS/IN 1
TDO/IN 2
GND
VCC
NC
1
I/O
Signal Name Description
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2064VE-200LJ44 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2064VE-200LT100 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2064VE-200LT44 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2064VL-135LT44 | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2064VL-100LB100 | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2064VE-135LTN100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064VE-135LTN100I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064VE-135LTN44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064VE-135LTN44I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064VE-200LB100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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