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參數(shù)資料
| 型號： | ISPLSI2032-110LT48 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 13 ns, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ISPLSI2032-110LT48 |
Specifications
ispLSI 2032/A
8
USEispLS 2032EFORNEWDESGNS
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Internal Timing Parameters
1
Over Recommended Operating Conditions
t
io
t
din
GRP
UNITS
-110
MIN.
-80
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
21 Dedicated Input Delay
–
–
–
–
2.2
4.8
ns
ns
t
grp
GLB
t
4ptbpc
t
4ptbpr
22 GRP Delay
–
–
2.6
ns
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
Outputs
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
28 GLB Register Bypass Delay
–
–
–
–
–
–
–
–
8.8
9.2
10.2
0.0
ns
ns
ns
ns
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
–
–
0.1
6.0
–
–
ns
ns
31 GLB Register Clock to Output Delay
–
–
0.4
ns
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
–
–
–
–
–
–
2.2
8.8
12.8
9.5
ns
ns
ns
ns
5.5
t
ob
t
sl
t
oen
t
odis
t
goe
Clocks
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
–
–
–
–
–
–
–
–
–
–
2.4
10.0
6.4
6.4
5.6
ns
ns
ns
ns
ns
1.7
3.4
1.7
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
–
–
–
–
7.2
7.2
ns
ns
6.2
6.8
7.5
0.1
4.9
4.8
0.5
4.0
0.6
1.8
5.9
7.1
7.0
4.0
36 ORP Delay
37 ORP Bypass Delay
–
–
–
–
2.1
0.6
ns
ns
1.5
0.5
1.2
10.0
4.0
4.0
3.0
t
gy0
t
gy1/2
Global Reset
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
3.2
3.2
4.6
4.6
4.6
4.6
ns
ns
3.2
3.2
t
gr
45 Global Reset to GLB
–
–
12.8
ns
9.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2032-110LT48I | In-System Programmable High Density PLD |
| ISPLSI2032-135LJ | In-System Programmable High Density PLD |
| ISPLSI2032-135LJI | In-System Programmable High Density PLD |
| ISPLSI2032-135LT44 | In-System Programmable High Density PLD |
| ISPLSI2032-135LT44I | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032-110LT48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI2032-135LJ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2032-135LJI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2032-135LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI-2032-135LT44 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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