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參數(shù)資料
| 型號： | ISPLSI2032-110LT44 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 13 ns, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ISPLSI2032-110LT44 |
Specifications
ispLSI 2032/A
5
USEispLS 2032EFORNEWDESGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-150
MIN.
–
154
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
1
4
1
tsu2 + tco1
( )
-135
MIN.
–
137
MAX.
8.0
MAX.
10.0
DESCRIPTION
#
2
PARAMETER
A
A
Data Prop. Delay
Clk Frequency with Internal Feedback
ns
MHz
–
–
–
–
–
A
–
4
5
6
7
8
Clk Frequency with Ext. Feedback
Clk Frequency, Max. Toggle
GLB Reg Setup Time before Clk, 4 PT Bypass
GLB Reg. Clk to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk, 4 PT Bypass
–
–
–
–
–
–
MHz
MHz
ns
ns
ns
–
–
0.0
–
–
–
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clk
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
4.5
–
0.0
–
4.5
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
18 Ext. Synchronous Clk Pulse Duration, High
19 Ext. Synchronous Clk Pulse Duration, Low
3.0
3.0
–
–
–
–
ns
ns
111
167
3.0
4.5
–
–
5.0
–
8.0
–
11.0
11.0
5.0
5.0
-180
MIN. MAX.
–
180
7.5
–
–
–
–
–
0.0
4.0
–
0.0
–
4.0
–
–
–
–
2.5
2.5
–
–
125
200
3.0
4.0
–
–
4.5
–
7.0
–
10.0
10.0
5.0
5.0
100
167
4.0
0.0
5.5
0.0
5.0
3.0
3.0
4.5
5.5
10.0
12.0
12.0
6.0
6.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2032-110LT44I | In-System Programmable High Density PLD |
| ISPLSI2032-110LT48 | In-System Programmable High Density PLD |
| ISPLSI2032-110LT48I | In-System Programmable High Density PLD |
| ISPLSI2032-135LJ | In-System Programmable High Density PLD |
| ISPLSI2032-135LJI | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032-110LT44I | 制造商:Rochester Electronics LLC 功能描述:ISPLSI 2000 1K GATES 32 MC 125MHZ IND EECMOS 5V 44 TQFP - Bulk |
| ispLSI2032-110LT48 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2032-110LT48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI2032-135LJ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2032-135LJI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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