參數(shù)資料
型號(hào): ISPLSI1032E-80LT
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: In-System Programmable High Density PLD
中文描述: EE PLD, 15 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 12/16頁
文件大?。?/td> 164K
代理商: ISPLSI1032E-80LT
12
Specifications
ispLSI 1032E
USEispLS 1032EAFORNEWDESGNS
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I is sensitive to operating
conditions and the program in the device, the actual I should be verified.
Maximum GRP Delay vs GLB Loads
GLB Load
3.0
5.0
8
16
4.0
4
2.0
6.0
GRP/GLB/1032E
ispLSI 1032E-70
ispLSI 1032E-90/100
ispLSI 1032E-80
ispLSI 1032E-125
1.0
Power Consumption
Figure 3. Typical Device Power Consumption vs fmax
Power consumption in the ispLSI 1032E device depends
on two primary factors: the speed at which the device is
operating, and the number of product terms used. Figure
3 shows the relationship between power and operating
speed.
0127/1032E
f
max (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25
°
C
100
200
300
0
20
40
60
80
100
I
C
ispLSI 1032E
250
150
350
125
I can be estimated for the ispLSI 1032E using the following equation:
I (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
CC
CC
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