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參數(shù)資料
| 型號： | ISPLSI1032E-125LJ |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 301K |
| 代理商： | ISPLSI1032E-125LJ |
6
Specifications
ispLSI and pLSI 1032E
–
9.0
NWEGS
15.0
–
–
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model
in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/1032E
1
4
3
1
( )
-70
MIN. MAX.
–
–
70.0
DESCRIPTION
#
2
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
15.0
17.5
ns
ns
MHz
–
–
–
–
4
5
6
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock,4 PT Bypass
–
–
–
MHz
MHz
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
–
ns
–
–
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
–
–
–
–
–
–
–
–
t
wh
t
wl
t
su3
t
h3
–
–
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
5.0
5.0
ns
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
ns
56.0
100
9.0
0.0
11.0
0.0
10.0
4.0
0.0
7.0
8.0
15.0
18.0
18.0
12.0
12.0
–
–
( )
1
-90
MIN. MAX.
–
–
90.0
10.0
12.5
–
–
–
–
0.0
8.5
–
0.0
–
6.5
–
–
4.0
4.0
3.5
–
0.0
–
69.0
125
7.5
6.0
–
–
7.0
–
13.5
–
15.0
–
–
-80
MIN. MAX.
–
–
80.0
12.0
15.0
–
–
–
–
–
–
–
–
–
–
–
–
4.5
4.5
–
–
61.0
111
8.5
0.0
10.0
0.0
8.0
3.5
0.0
6.5
7.5
14.0
16.5
16.5
10.0
10.0
–
–
External Timing Parameters
Over Recommended Operating Conditions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ispLSI1032EA-100LT100 | In-System Programmable High Density PLD |
| ISPLSI1032EA-200LT100 | In-System Programmable High Density PLD |
| ispLSI1032EA-125LT100 | In-System Programmable High Density PLD |
| ISPLSI1032EA | In-System Programmable High Density PLD |
| ISPLSI1032EA-170LT100 | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1032E125LJI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E125LJN | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ispLSI1032E-125LJN | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1032E125LJNI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E125LT | 制造商:LATT 功能描述: |
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