參數(shù)資料
型號(hào)： ISPLSI1024EA-100LT100
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： In-System Programmable High Density PLD
中文描述： EE PLD, 12.5 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 11/13頁(yè)
文件大?。?/td> 162K
代理商： ISPLSI1024EA-100LT100
11
Specifications
ispLSI 1024EA
Pin Description
Input - Controls the operation of the ISP state machine.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
NAME
Table 2-0002A/1024EA
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
Y1
Y0
TMS
Ground (GND)
GND
GOE 0/IN 4
1
GOE 1/IN 5
1
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
TDI
TDO
Output - Functions as an output pin to read serial shift register data.
TCK
Input - Functions as a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
RESET
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Y2
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
Y3
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
TQFP PIN
NUMBERS
20,
28,
32,
43,
47,
55,
70,
78,
82,
93,
97,
5,
Vcc
VCC
2,
25,
39,
52,
75,
88,
15,
62,
11,
66,
12,
26,
49,
63,
76,
99,
21,
29,
33,
44,
48,
56,
71,
79,
83,
94,
98,
6,
36,
89,
40,
85,
13,
27,
50,
64,
77,
100
22,
30,
34,
45,
53,
57,
72,
80,
84,
95,
3,
7
37,
90
41,
86
NC
2
No Connect
Supply voltage for output drivers, 5V or 3.3V.
VCCIO
1,
24,
38,
51,
74,
87,
19,
23,
31,
42,
46,
54,
69,
73,
81,
92,
96,
4,
67
9
68
8
91
18
35
58
17
60
59
14,
61,
10,
65,
16
相關(guān)PDF資料
PDF描述
ISPLSI1024EA-125LT100 In-System Programmable High Density PLD
ISPLSI1024EA-200LT100 In-System Programmable High Density PLD
ISPLSI1032-80LJ In-System Programmable High Density PLD
ISPLSI1032-80LT In-System Programmable High Density PLD
ISPLSI1032-90LJ In-System Programmable High Density PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI1024EA-125LT100 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1024EA-200LT100 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1032 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1032-50LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
ISPLSI1032-60 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
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