Specifications ispLSI 1048 5 18 23 – 12 – 14 – 17 – 20 – 71.4 41.7 83 9 – 0 12 – 0 – 10 – 6 2 6.5 15 20 – 10 – 12 – 17 – 18 – 1. Unless noted o" />
參數(shù)資料
型號(hào): ISPLSI 1048-70LQ
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 10/13頁
文件大?。?/td> 0K
描述: IC PLD ISP 96I/O 15NS 120PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ispLSI® 1000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 18.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 48
門數(shù): 8000
輸入/輸出數(shù): 96
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-BQFP
供應(yīng)商設(shè)備封裝: 120-PQFP(28x28)
包裝: 托盤
其它名稱: ISPLSI1048-70LQ
Specifications ispLSI 1048
5
18
23
12
14
17
20
71.4
41.7
83
9
0
12
0
10
6
2
6.5
15
20
10
12
17
18
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
MIN. MAX.
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
ns
MHz
ns
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
ten
tdis
twh
twl
tsu5
th5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
A
A
B
C
DESCRIPTION1
PARAMETER
#
2
UNITS
TEST 5
COND.
1
tsu2 + tco1
(
)
MIN.
53.6
31.3
71.4
12
0
16
0
13
7
2.7
8.7
24
30.7
16
18.7
22.7
26.7
-50
MIN. MAX.
80
50
100
7
0
10
0
10
5
2
6.5
-80
Table 2- 0030A-48/80,70,50
MAX.
-70
External Timing Parameters
Over Recommended Operating Conditions
ALL
DEVICES
DISCONTINUED
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參數(shù)描述
ispLSI1048-70LQ 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1048-70LT 制造商:Lattice Semiconductor Corporation 功能描述:
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