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參數(shù)資料
| 型號： | ISPLSI 1048-50LQI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 96I/O 18NS 120PQFP |
| 標準包裝： | 24 |
| 系列： | ispLSI® 1000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 24.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 邏輯元件/邏輯塊數(shù)目： | 48 |
| 門數(shù)： | 8000 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-BQFP |
| 供應商設備封裝： | 120-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI1048-50LQI |
Specifications ispLSI 1048
10
Pin Description
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
V
CC
GND
46, 76,106, 16
VCC
15, 45, 77, 107
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
20, 21, 22, 23, 24, 25,
I/O 6 - I/O 11
26, 27, 28, 29, 30, 31,
I/O 12 - I/O 17
32, 33, 34, 35, 36, 37,
I/O 18 - I/O 23
38, 39, 40, 41, 42, 43,
I/O 24 - I/O 29
49, 50, 51, 52, 53, 54,
I/O 30 - I/O 35
55, 56, 57, 58, 59, 60,
I/O 36 - I/O 41
61, 62, 63, 64, 65, 66,
I/O 42 - I/O 47
67, 68, 69, 70, 71, 72,
I/O 48 - I/O 53
80, 81, 82, 83, 84, 85,
I/O 54 - I/O 59
86, 87, 88, 89, 90, 91,
I/O 60 - I/O 65
92, 93, 94, 95, 96, 97,
I/O 66 - I/O 71
98, 99,100,101,102,103,
I/O 72 - I/O 77
109,110,111,112,113,114,
I/O 78 - I/O 83
115,116,117,118,119,120,
I/O 84 - I/O 89
1,
2,
3,
4
5,
6,
I/O 90 - I/O 95
7,
8,
9, 10, 11, 12
IN 4
48,
IN 6 - IN 11
79,104,105, – 108, 13
Dedicated input pins to the device. (IN 2 and IN 9 not available)
RESET
18
Y0
14
Y1
78
Y2
75
Y3
74
Table 2- 0002C-48-isp
DESCRIPTION
NAME
PQFP PIN NUMBERS
ispEN
17
SDI/IN 01
19
MODE/IN 11
44
SDO/IN 31
47
SCLK/IN 51
73
1. Pins have dual function capability.
ALL
DEVICES
DISCONTINUED
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI1048-50LQI | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI1048-70LQ | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1048-70LT | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI1048-80LQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1048C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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