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參數(shù)資料
| 型號(hào)： | ISPL1048E-100LT |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 158K |
| 代理商： | ISPL1048E-100LT |
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Specifications
ispLSI 1048E
7
Internal Timing Parameters
1
U40NES
–
–
–
4.0
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1048E
Inputs
UNITS
-100
MIN.
-90
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
–
–
–
–
0.5
2.5
–
–
5.0
5.0
2.9
ns
ns
ns
ns
ns
ns
ns
t
grp1
t
grp4
t
grp8
t
grp16
t
grp48
29 GRP Delay, 1 GLB Load
–
–
2.2
ns
GLB
t
4ptbpc
t
4ptbpr
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
36 1 Product Term/XOR Path Delay
37 20 Product Term/XOR Path Delay
38 XOR Adjacent Path Delay
39 GLB Register Bypass Delay
–
–
–
–
–
–
–
–
6.5
6.5
7.3
0.4
ns
ns
ns
ns
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
–
–
0.1
6.4
–
–
ns
ns
42 GLB Register Clock to Output Delay
–
–
2.0
ns
3
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
–
–
–
6.3
5.0
5.7
5.2
ns
ns
ns
ns
0.3
2.3
–
–
5.0
5.0
2.7
GRP
1.9
34 4 Product Term Bypass Path Delay (Combinatorial)
–
–
5.4
ns
4.6
5.8
6.3
1.0
5.3
35 4 Product Term Bypass Path Delay (Registered)
–
–
6.3
ns
5.3
0.5
5.3
2.5
6.2
4.5
7.2
4.7
3.5
47 ORP Delay
48 ORP Bypass Delay
–
–
–
–
1.0
0.0
ns
ns
1.0
0.0
3.5
0.0
–
–
–
4.0
-0.5
–
–
–
30 GRP Delay, 4 GLB Loads
–
–
2.4
ns
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 48 GLB Loads
–
–
–
–
–
–
2.7
3.3
5.7
ns
ns
ns
2.4
2.6
3.0
5.4
-125
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3
1.9
–
–
4.6
4.6
2.3
1.8
–
3.6
5.0
5.0
0.4
3.9
–
4.0
0.1
4.5
2.3
4.9
3.9
5.4
4.0
2.9
–
–
1.0
0.0
3.0
0.0
–
–
–
–
–
–
–
2.0
2.3
2.8
4.9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPL1048E-100LTI | High-Density Programmable Logic |
| ISPL1048E-125LQ | High-Density Programmable Logic |
| ISPL1048E-90LQI | High-Density Programmable Logic |
| ISPL1048E-70LQI | High-Density Programmable Logic |
| ISPL1048E-50LQI | High-Density Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPL1048E-100LTI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-125LQ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-125LQI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-125LT | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPL1048E-125LTI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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