參數(shù)資料
型號(hào): ISPGDS14-7J
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: in-system programmable Generic Digital SwitchTM
中文描述: EE PLD, 7.5 ns, PQCC20
封裝: PLASTIC, LCC-20
文件頁數(shù): 5/8頁
文件大?。?/td> 104K
代理商: ISPGDS14-7J
Specifications
ispGDS
5
Vcc
C0
C1
C2
Switch
Matrix
0 1
1 0
1 1
0 0
4:1 MUX
Closed only when C0=1 and C1=0
Configuration for Active High Output
- C0 = 0.
- C1 = 1.
- C2 = 1.
Configuration for Dedicated Input
- C0 = 1.
- C1 = 0.
- C2 = 1.
Configuration for Active Low Output
- C0 = 0.
- C1 = 0.
- C2 = 1.
Configuration for Fixed TTL High Output
- C0 = 0.
- C1 = 1.
- C2 = 0.
Configuration for Fixed TTL Low Output
- C0 = 0.
- C1 = 0.
- C2 = 0.
Note 1: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Note 2: The default configuration for unused pins is for all configuration bits set to one, which produces a tri-stated output.
I/O Macrocell
I/O Macrocell Configurations
From
Switch
Matrix
From
Switch
Matrix
Vcc
To
Switch
Matrix
相關(guān)PDF資料
PDF描述
ISPGDS14-7P in-system programmable Generic Digital SwitchTM
ISPGDS18-7P in-system programmable Generic Digital SwitchTM
ISPGDS22 in-system programmable Generic Digital SwitchTM
ISPGDS22-7J in-system programmable Generic Digital SwitchTM
ISPGDS22-7P in-system programmable Generic Digital SwitchTM
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