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參數(shù)資料
| 型號： | ISP1123NB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Universal Serial Bus compound hub |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 34/49頁 |
| 文件大?。?/td> | 1155K |
| 代理商： | ISP1123NB |
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Philips Semiconductors
ISP1123
USB compound hub
Preliminary specification
Rev. 01 — 5 October 1999
34 of 49
9397 750 06325
Philips Electronics N.V. 1999. All rights reserved.
[1]
Operating modes 0, 1, 4 and 5; see
Table 4
.
[1]
[2]
[3]
Test circuit; see
Figure 23
.
Excluding the first transition from Idle state.
Characterized only, not tested. Limits guaranteed by design.
Table 31: Dynamic characteristics: overcurrent sense pins
V
CC
= 4.0 to 5.5 V; V
GND
= 0 V; T
amb
=
40 to
+
85
°
C; unless otherwise specified.
Symbol
Parameter
t
trip
overcurrent trip response time
from OCn LOW to PSWn HIGH
Conditions
see
Figure 15
Min
Typ
Max
Unit
[1]
-
-
15
ms
Table 32: Dynamic characteristics: analog I/O pins (D
+
, D
); full-speed mode
[1]
V
CC
= 4.0 to 5.5 V; V
GND
= 0 V; T
amb
=
40 to
+
85
°
C; C
L
= 50 pF; R
PU
= 1.5 k
on D
+
to V
TERM
.; unless otherwise specified.
Symbol
Parameter
Conditions
Driver characteristics
t
FR
rise time
C
L
= 50 pF;
10 to 90% of
|
V
OH
V
OL
|
t
FF
fall time
C
L
= 50 pF;
10 to 90% of
|
V
OH
V
OL
|
FRFM
differential rise/fall time
matching (t
FR
/t
FF
)
V
CRS
output signal crossover voltage
Data source timing
t
DJ1
source differential jitter for
consecutive transitions
t
DJ2
source differential jitter for
paired transitions
t
FEOPT
source EOP width
see
Figure 17
t
FDEOP
source differential data-to-EOP
transition skew
Receiver timing
t
JR1
receiver data jitter tolerance for
consecutive transitions
t
JR2
receiver data jitter tolerance for
paired transitions
t
FEOPR
receiver SE0 width
accepted as EOP;
see
Figure 17
t
FST
width of SE0 during differential
transition
see
Figure 19
Hub timing (downstream ports configured as full-speed)
t
FHDD
hub differential data delay
(without cable)
C
L
= 0 pF
t
FSOP
data bit width distortion after
SOP
t
FEOPD
hub EOP delay relative to t
HDD
see
Figure 21
t
FHESK
hub EOP output width skew
see
Figure 21
Min
Typ
Max
Unit
4
-
20
ns
4
-
20
ns
[2]
90
-
111.11
%
[2] [3]
1.3
-
2.0
V
see
Figure 16
[2] [3]
3.5
-
+
3.5
ns
see
Figure 16
[2] [3]
4
-
+
4
ns
[3]
160
-
-
175
+
5
ns
ns
see
Figure 17
[3]
2
see
Figure 18
[3]
18.5
-
+
18.5
ns
see
Figure 18
[3]
9
-
+
9
ns
[3]
82
-
-
ns
rejected as EOP;
[3]
-
-
14
ns
see
Figure 20
;
[3]
-
-
44
ns
see
Figure 20
[3]
5
-
+
5
ns
[3]
0
-
-
15
+
15
ns
ns
[3]
15
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|---|---|
| ISP1130 | Universal Serial Bus compound hub with integrated keyboard controller |
| ISP1130DL | Universal Serial Bus compound hub with integrated keyboard controller |
| ISP1130N | Universal Serial Bus compound hub with integrated keyboard controller |
| ISP1160 | Embedded Universal Serial Bus Host Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1130 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus compound hub with integrated keyboard controller |
| ISP1130DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus compound hub with integrated keyboard controller |
| ISP1130N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus compound hub with integrated keyboard controller |
| ISP1160 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Embedded Universal Serial Bus Host Controller |
| ISP1160BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Embedded Universal Serial Bus Host Controller |
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