參數(shù)資料
型號: ISP1123D
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Universal Serial Bus compound hub
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO32
封裝: 7.50 MM, PLASTIC, SO-32
文件頁數(shù): 38/49頁
文件大?。?/td> 1155K
代理商: ISP1123D
Philips Semiconductors
ISP1123
USB compound hub
Preliminary specification
Rev. 01 — 5 October 1999
38 of 49
9397 750 06325
Philips Electronics N.V. 1999. All rights reserved.
[1]
[2]
f
SCL
=
1
64
f
XTAL
.
Rise time is determined by C
b
and pull-up resistor value R
p
(typ. 4.7 k
).
Full-speed timing symbols have a subscript prefix ‘F’, low-speed timings a prefix ‘L.
Fig 21. Hub EOP delay and EOP skew.
handbook, full pagewidth
MGR778
tEOP
+
tEOP
tEOP
+
tEOP
crossover
point
extended
crossover
point
extended
EOP delay:
tEOP = max (tEOP
, tEOP
+
)
EOP delay relative to tHDD:
tEOPD = tEOP
tHDD
EOP skew:
tHESK = tEOP
+
tEOP
(A) downstream EOP delay
(B) upstream EOP delay
upstream
differential
data lines
downstream
port
crossover
point
extended
crossover
point
extended
upstream
end of cable
downstream
differential
data lines
0 V
+
3.3 V
0 V
Table 34: Dynamic characteristics: I
2
C-bus pins (SDA, SCL)
V
CC
and T
amb
within recommended operating range; V
DD
=
+5 V; V
SS
= V
GND
; V
IL
and V
IH
between V
SS
and V
DD
.
Symbol
Parameter
Conditions
f
SCL
SCL clock frequency
f
XTAL
= 6 MHz
t
BUF
bus free time
t
SU;STA
START condition set-up time
t
HD;STA
hold time START condition
t
LOW
SCL LOW time
t
HIGH
SCL HIGH time
t
r
SCL and SDA rise time
t
f
SCL and SDA fall time
t
SU;DAT
data set-up time
t
HD;DAT
data hold time
t
VD;DAT
SCL LOW to data out valid
time
t
SU;STO
STOP condition set-up time
C
b
capacitive load for each bus
line
Min
0
4.7
250
4.0
4.7
4.0
Typ
93.75
[1]
-
-
-
-
-
-
-
-
-
-
Max
100
-
-
-
-
-
1000
300
-
-
0.4
Unit
kHz
μ
s
ns
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
μ
s
[2]
-
-
250
0
-
4.0
-
-
-
-
400
μ
s
pF
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ISP1160 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Embedded Universal Serial Bus Host Controller