參數(shù)資料
型號: ISP1106W
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: GT 5C 5#16 PIN PLUG
中文描述: LINE TRANSCEIVER, PBCC16
封裝: LEAD AND HALOGEN FREE, 3 X 3 MM, 0.65 MM HEIGHT, PLASTIC, MO-217, SOT-639-2, HBCC-16
文件頁數(shù): 5/24頁
文件大?。?/td> 588K
代理商: ISP1106W
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
Product data
Rev. 06 — 30 November 2001
5 of 24
9397 750 08872
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
6.2 Pin description
Table 3:
Symbol
[1]
Pin description
Pin
ISP1105
HBCC16
1
Type
Description
ISP1106/7
HBCC16
1
ISP1106/7
TSSOP16
3
OE
I
input for output enable (CMOS level with respect to V
CC(I/O)
,
active LOW); enables the transceiver to transmit data on
the USB bus
differential data receiver output (CMOS level with respect to
V
CC(I/O)
); driven LOW when input SUSPND is HIGH; the
output state of RCV is preserved and stable during an SE0
condition
single-ended D
+
receiver output (CMOS level with respect
to V
CC(I/O)
); for external detection of single-ended zero
(SE0), error conditions, speed of connected device; driven
HIGH when no supply voltage is connected to V
CC(5.0)
and
V
reg(3.3)
single-ended D
receiver output (CMOS level with respect
to V
CC(I/O)
); for external detection of single-ended zero
(SE0), error conditions, speed of connected device; driven
HIGH when no supply voltage is connected to V
CC(5.0)
and
V
reg(3.3)
suspend input (CMOS level with respect to V
CC(I/O)
); a
HIGH level enables low-power state while the USB bus is
inactive and drives output RCV to a LOW level
mode input (CMOS level with respect to V
CC(I/O)
); a HIGH
level enables the differential input mode (VPO, VMO)
whereas a LOW level enables a single-ended input mode
(VO, FSE0). see
Table 5
and
Table 6
ground supply
supply voltage for digital I/O pins (1.65 to 3.6 V). When
V
CC(I/O)
is not connected, the (D
+,
D
) pins are in
three-state. This supply pin is totally independent of
V
CC(5.0)
and V
reg(3.3)
and must never exceed the V
reg(3.3)
voltage.
speed selection input (CMOS level with respect to V
CC(I/O)
);
adjusts the slew rate of differential data outputs D
+
and D
according to the transmission speed:
LOW:
low-speed (1.5 Mbit/s)
HIGH:
full-speed (12 Mbit/s)
negative USB data bus connection (analog, differential); for
low-speed mode connect to pin V
pu(3.3)
via a 1.5 k
resistor
positive USB data bus connection (analog, differential); for
full-speed mode connect to pin V
pu(3.3)
via a 1.5 k
resistor
driver data input (CMOS level with respect to V
CC(I/O)
,
Schmitt trigger); see
Table 5
and
Table 6
driver data input (CMOS level with respect to V
CC(I/O)
,
Schmitt trigger); see
Table 5
and
Table 6
RCV
2
2
4
O
VP
3
3
5
O
VM
4
4
6
O
SUSPND
5
5
7
I
MODE
6
I
GND
V
CC(I/O)
-
[2]
7
6
7
8
9
-
-
SPEED
8
8
10
I
D
9
9
11
AI/O
D
+
10
10
12
AI/O
VPO/VO
11
11
13
I
VMO/FSE0
12
12
14
I
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