參數(shù)資料
型號： ISP1105W
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Advanced Universal Serial Bus transceivers
中文描述： LINE TRANSCEIVER, PBCC16
封裝： LEAD AND HALOGEN FREE, 3 X 3 MM, 0.65 MM HEIGHT, PLASTIC, MO-217, SOT-639-2, HBCC-16
文件頁數(shù)： 13/24頁
文件大?。?/td> 588K
代理商： ISP1105W
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
Product data
Rev. 06 — 30 November 2001
13 of 24
9397 750 08872
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
10. Dynamic characteristics
Table 16:
V
CC
= 4.0 to 5.5 V or V
reg(3.3)
= 3.0 to 3.6 V; V
CC(I/O)
= 1.65 to 3.6 V; V
GND
= 0 V; see
Table 10
for valid voltage level
combinations; T
amb
=
40 to
+
85
°
C; unless otherwise specified.
Symbol
Parameter
Conditions
Driver characteristics
Full-speed mode (SPEED = HIGH)
t
FR
rise time
C
L
= 50 to 125 pF;
10 to 90% of
|
V
OH
V
OL
|
;
see
Figure 5
t
FF
fall time
C
L
= 50 to 125 pF;
90 to 10% of
|
V
OH
V
OL
|
;
see
Figure 5
FRFM
differential rise/fall time
matching (t
FR
/t
FF
)
from Idle state
V
CRS
output signal crossover
voltage
from Idle state; see
Figure 8
Low-speed mode (SPEED = LOW)
t
LR
rise time
C
L
= 50 to 600 pF;
10 to 90% of
|
V
OH
V
OL
|
;
see
Figure 5
t
LF
fall time
C
L
= 50 to 600 pF;
90 to 10% of
|
V
OH
V
OL
|
;
see
Figure 5
LRFM
differential rise/fall time
matching (t
LR
/t
LF
)
from Idle state
V
CRS
output signal crossover
voltage
from idle state; see
Figure 8
Driver timing
Full-speed mode (SPEED = HIGH)
t
PLH(drv)
driver propagation delay
LOW-to-HIGH; see
Figure 8
t
PHL(drv)
(VO/VPO, FSE0/VMO to
D
+
,D
)
t
PHZ
driver disable delay
HIGH-to-OFF; see
Figure 6
t
PLZ
(OE to D
+
,D
)
LOW-to-OFF; see
Figure 6
t
PZH
driver enable delay
OFF-to-HIGH; see
Figure 6
t
PZL
(OE to D
+
,D
)
OFF-to-LOW; see
Figure 6
Low-speed mode (SPEED = LOW)
Not specified
: low-speed delay timings are dominated by the slow rise/fall times t
LR
and t
LF
.
Dynamic characteristics: analog I/O pins (D
+
, D
)
[1]
Min
Typ
Max
Unit
4
-
20
ns
4
-
20
ns
excluding the first transition
90
-
111.1
%
excluding the first transition
[2]
1.3
-
2.0
V
75
-
300
ns
75
-
300
ns
excluding the first transition
80
-
125
%
excluding the first transition
[2]
1.3
-
2.0
V
-
-
-
-
18
18
ns
ns
HIGH-to-LOW; see
Figure 8
-
-
-
-
-
-
-
-
15
15
15
15
ns
ns
ns
ns
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