參數(shù)資料
型號: ISP1105
廠商: NXP Semiconductors N.V.
英文描述: Advanced Universal Serial Bus transceivers
中文描述: 先進(jìn)的通用串行總線收發(fā)器
文件頁數(shù): 7/24頁
文件大小: 588K
代理商: ISP1105
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
Product data
Rev. 06 — 30 November 2001
7 of 24
9397 750 08872
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
7.2 Operating functions
[1]
[2]
VP = VM = H indicates the sharing mode (V
CC(5.0)
/V
reg(3.3)
is disconnected).
RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during
the SE0 period.
7.3 Power supply configurations
The ISP1105/1106/1107 can be used with different power supply configurations,
which can be changed dynamically. An overview is given in
Table 9
.
Normal mode —
Both V
CC(I/O)
and V
CC(5.0)
or (V
CC(5.0)
and V
reg(3.3)
) are connected.
For 5 V operation, V
CC(5.0)
is connected to a 5 V source (4.0 to 5.5 V). The internal
voltage regulator then produces 3.3 V for the USB connections. For 3.3 V operation,
both V
CC(5.0)
and V
reg(3.3)
are connected to a 3.3 V source (3.0 to 3.6 V). V
CC(I/O)
is
independently connected to a voltage source (1.65 V to 3.6 V), depending on the
supply voltage of the external circuit.
Disable mode —
V
CC(I/O)
is not connected, V
CC(5.0)
or (V
CC(5.0)
and V
reg(3.3)
) are
connected. In this mode, the internal circuits of the ISP1105/1106/1107 ensure that
the (D
+
, D
) pins are in three-state and the power consumption drops to the
low-power (suspended) state level. Some hysteresis is built into the detection of
V
CC(I/O)
lost.
Sharing mode —
V
CC(I/O)
is connected, (V
CC(5.0)
and V
reg(3.3)
) are not connected. In
this mode, the (D
+
, D
) pins are made three-state and the ISP1105/1106/1107 allows
external signals of up to 3.6 V to share the (D
+,
D
) lines. The internal circuits of the
ISP1105/1106/1107 ensure that virtually no current (maximum 10
μ
A) is drawn via
the (D
+,
D
) lines. The power consumption through pin V
CC(I/O)
drops to the
Table 5:
Driving function using single-ended input data interface (OE = L) [for
ISP1107 and ISP1105 (MODE = L)]
VO
L
H
L
H
FSE0
L
L
H
H
Data
differential logic 0
differential logic 1
SE0
SE0
Table 6:
Driving function using differential input data interface (OE = L) [for ISP1106
and ISP1105 (MODE = H)]
VPO
L
H
L
H
VMO
L
L
H
H
Data
SE0
differential logic 1
differential logic 0
illegal state
Table 7:
Receiving function (OE = H)
(D
+
, D
)
differential logic 0
differential logic 1
SE0
RCV
L
H
RCV*
[2]
VP
[1]
L
H
L
VM
[1]
H
L
L
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