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參數(shù)資料
| 型號(hào)： | ISO806 |
| 英文描述： | Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 隔離12位采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 147K |
| 代理商： | ISO806 |
8
ISO806
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the
Calibra-
tion
section).
The input impedance, summarized in Table II, results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors
used for each input range (see Figure 4). The input resistor
divider network provides inherent overvoltage protection
guaranteed to at least
±
25V.
Analog inputs above or below the expected range will yield
either positive full scale or negative full scale digital outputs
respectively. There will be no wrapping or folding over for
analog inputs outside the nominal range.
Note: (1) Full scale error includes offset and gain errors measured at both +FS
and –FS.
CALIBRATION
HARDWARE CALIBRATION
To calibrate the offset and gain of the ISO806 in hardware,
install the resistors shown in Figure 3a. Table VI lists the
hardware trim ranges relative to the input for each input
range.
SERIAL OUTPUT
The serial output can not be tri-stated and is always active.
INTERNAL DATA CLOCK (During A Conversion)
The R/C (pin 1) LOW will initiate conversion ‘n’ and
activate the internal data clock (typically 900kHz clock
rate). The ISO806 will output 12 bits of valid data, MSB
first, from conversion ‘n-1’ on SDATA (pin 28), synchro-
nized to 12 clock pulses output on DATACLK (pin 27). The
data will be valid on both the rising and falling edges of the
internal data clock. The rising edge of BUSY (pin 2) can be
used to latch the data. After the 12th clock pulse, DATACLK
will remain LOW until the next conversion is initiated,
SDATA will also go LOW.
INPUT RANGES
The ISO806 offers three input ranges: standard
±
10V and
0-5V, and a 0-4V range for complete, single supply systems.
Figures 3a and 3b show the necessary circuit connections for
implementing each input range and optional offset and gain
adjust circuitry. Offset and full scale error
(1)
specifications
are tested and guaranteed with the fixed resistors shown in
Figure 3b. Adjustments for offset and gain are described in
the
Calibration
section of this data sheet.
1
MSB Valid
R/C
DATACLK
SDATA
BUSY
t
7
+ t
8
t
16
t
15
t
14
t
13
2
3
11
12
Bit 10 Valid
Bit 1 Valid
Bit 9 Valid
LSB Valid
1
MSB Valid
2
Bit 10 Valid
(Results from previous conversion.)
FIGURE 2. Serial Data Timing.
±
10V
0-4V
0-5V
FIGURE 3a. Circuit Diagrams (With Hardware Trim).
200
12
14
15
16
17
AGND
REF
CAP
R2
IN
R1
IN
+
+
2.2μF
2.2μF
1M
+5V
50k
+5V
100
33.2k
50k
V
IN
200
12
14
15
16
17
AGND
REF
CAP
R2
IN
R1
IN
+
+
2.2μF
2.2μF
33.2k
100
V
IN
1M
+5V
50k
50k
200
12
14
15
16
17
AGND
REF
CAP
R2
IN
R1
IN
+
+
2.2μF
2.2μF
1M
+5V
50k
50k
33.2k
100
V
IN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISO806P | Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ISO807P | Isolated 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ISO807 | |
| ISO807 | Isolated 16-Bit Sampling Analog-To-Digital Converter(隔離的16位采樣A\D轉(zhuǎn)換器) |
| ISO808 | Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISO806P | 制造商:BB 制造商全稱:BB 功能描述:Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ISO807 | 制造商:BB 制造商全稱:BB 功能描述:Isolated 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ISO807P | 制造商:BB 制造商全稱:BB 功能描述:Isolated 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ISO808 | 制造商:BB 制造商全稱:BB 功能描述:Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| ISO808P | 制造商:BB 制造商全稱:BB 功能描述:Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
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