9
ISO213
number of ISO213s. See Figure 6, 7, and 8 for connections
in multiple ISO213 installations.
FIGURE 5. Equivalent Circuit, Clock Input/Output. Inverters
are CMOS.
0V +15V Sync
+V
Clk Out
Clk In
Com 2
CC
ISO213P/Slave
+V
Clk Out
Clk In
Com 2
CC
ISO213P/Slave
+V
Clk Out
Clk In
Com 2
CC
ISO213P/Master
FIGURE 7. Isolating the Clk Out Node.
FIGURE 6. Oscillator Connections for Synchronous Opera-
tion in Multiple ISO213P Installations.
NOISE
Output noise is generated by residual components of the
25kHz carrier that have not been removed from the signal.
This noise may be reduced by adding an output low-pass
filter (see Figure 9). The filter time constant should be set
below the carrier frequency. The output from ISO213 is a
switched capacitor and requires a high impedance load to
prevent degradation of linearity. Loads of less than 1M
will cause an increase in noise at the carrier frequency and
will appear as ripple in the output waveform. Since the
output signal power is generated from the input side of the
barrier, decoupling of the
±
V
SS
outputs will improve the
signal to noise ratio.
SYNCHRONIZATION
OF THE INTERNAL OSCILLATOR
ISO213 has an internal oscillator and associated timing
components, which can be synchronized. This alleviates the
requirement for an external high-power clock driver. The
typical frequency of oscillation is 50kHz. The internal clock
will start when power is applied to ISO213 and Clk In is not
connected.
Because the oscillator frequency of each ISO213 can be
marginally different, “beat” frequencies ranging from a few
Hz to a few kHz can exist in multiple amplifier applications.
The design of ISO213 accommodates “internal synchro-
nous” noise, but a synchronous beat frequency noise will not
be strongly attenuated, especially at very low frequencies if
it is introduced via the power, signal, or potential grounding
paths. To overcome this problem in systems where several
ISO213s are used, the design allows synchronization of each
oscillator in a system to one frequency. Do this by forcing
the timing node on the internal oscillator with an external
driver connected to Clk In (Figure 5). The driver may be an
external component with Series 4000 CMOS characteristics,
or one ISO213 in the system can be used as the master clock
for the system. An alternative where a specific frequency is
not required is to lock all ISO213s together by joining all
Clk Ins. This method can be used to lock an unlimited
FIGURE 4. Recommended Decoupling and Power Distribu-
tion.
Clamp
Diodes
Clock
In
+V
CC
Com 2
220pF
39k
Clock
Out
Power In
Track Resistance/Inductance
I
Ground Plane
100μF
10μF
0.1μF
0.1μF
0.1μF
0.1μF
10μF
10μF
I
I
Clk Out
Clk In
Clk In
Clk In
Clk In
S
R
S
22k
22k
22k
22k
22k
S
S
S
S
M
Clk Out
Clk In
Clk In
Clk In
Clk In
S
S
S
S
S
M