29 FN7853.1 June 17, 2011 D ev ic eCo nfig /Co ntr ol 73 output_mode_A Output Mode [7:5] 000 = LVDS 3mA (Default) 001 = LVDS 2mA 100 =" />
參數(shù)資料
型號： ISLA222P20IRZ
廠商： Intersil
文件頁數(shù)： 22/33頁
文件大小： 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 830mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA222P
29
FN7853.1
June 17, 2011
D
ev
ic
eCo
nfig
/Co
ntr
ol
73
output_mode_A
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
Output Format [2:0]
000 = Two’s Complement (Default)
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
00h
NOT reset by
Soft Reset
74
output_mode_B
DLL Range
0 = Fast
1 = Slow
Default=’0’
00h
NOT reset by
Soft Reset
75-B5
Reserved
B6
cal_status
Calibration
Done
Read Only
B7-BF
Reserved
De
vi
ce
T
est
C0
test_io
Output Test Mode [7:4]
User Test Mode [2:0]
0 = user pattern 1 only
1 = cycle pattern 1,3
2 = cycle pattern 1,3,5
3 = cycle pattern 1,3,5,7
4-7 = NA
00h
0 = Off (Note 14)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Reserved (Note15)
5-6 = Reserved
7 = Reserved (Note16)
8 = User Pattern (1 to 4 deep)
9 = Reserved
10 = Ramp
11-15 = Reserved
C1
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
C2
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
user_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
user_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
user_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
user_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
user_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
user_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
user_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
user_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
user_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
user_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
user_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
D0
user_patt8_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
D1-FF
Reserved
NOTES:
14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of
calibration. This behavior can be used as an option to determine calibration state.
15. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs on DDR Outputs.
16. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs on DDR Outputs.
SPI Memory Map (Continued)
ADDR.
(Hex)
PARAMETER NAME
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
DEF. VALUE
(HEX)
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