參數(shù)資料
型號(hào)： ISL98002CRZ-140
廠商： Intersil
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 0K
描述： IC VID DIGITIZER 3CHN AFE 72-QFN
標(biāo)準(zhǔn)包裝： 840
位數(shù)： 8
通道數(shù)： 3
功率（瓦特）： 525mW
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
封裝/外殼： 72-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤(pán)
24
FN6535.1
December 7, 2009
Reducing Power Dissipation
It is possible to reduce the total power consumption of the
ISL98002 in applications where power is a concern. There are
several techniques that can be used to reduce power
consumption:
Buffering Digital Outputs. Switching data output pins into a
capacitive bus can consume significant current. The higher
the capacitance on the external databus, the higher the
switching current. To minimize current consumption inside
the ISL98002, minimize bus capacitance and/or insert data
buffers such as the SN64AVC16827 between the ISL98002’s
data outputs and the external databus.
Internal Reference Frequency. The crystal frequency is
multiplied by the value in register 0x2B to generate an
internal high frequency reference clock. This internal
frequency should be set to 400MHz ±10% for minimum
power consumption. For example, for a 33MHz frequency at
XTALIN, register 0x2B should be set to a value of 0x0C to
minimize power.
Standby Mode
The ISL98002 can be placed into a low power standby mode
by writing a 0x0F to register 0x1B, powering down the triple
ADCs, the DPLL, and most of the internal clocks.
To allow input monitoring and mode detection during
power-down, the following blocks remain active:
Serial interface (including the crystal oscillator) to enable
register read/write activity
Activity and polarity detect functions (registers 0x01 and
0x02)
The HSYNCOUT and VSYNCOUT pins (for mode
detection)
Initialization
The ISL98002 initializes with default register settings for an
AC-coupled, RGB input.
Reset
The ISL98002 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the “Register Listing” beginning on
page 10. The external RESET pin duplicates the reset
function of the POR without having to cycle the power
supplies. The RESET pin does not need to be used in
normal operation and can be tied high.
ISL98002 Serial Communication
Overview
The ISL98002 uses a 2-wire serial bus for communication
with its host. SCL is the Serial Clock line, driven by the host,
and SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1. The Host selects the ISL98002 it wishes to communicate
with.
2. The Host writes the initial ISL98002 Configuration
Register address it wishes to write to or read from.
3. The Host writes to or reads from the ISL98002’s
Configuration Register. The ISL98002’s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in
Step 2, then repeat Step 3 28x, with each read returning
the next register value.
The ISL98002 has a 7-bit address on the serial bus. The
upper 6-bits are permanently set to 100110, with the lower
bit determined by the state of pin 29. This allows two
ISL98002s to be independently controlled while sharing the
same bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high
(see Figure 7). The ISL98002 continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been met.
The host then transmits the 7-bit serial address plus a R/W
bit, indicating if the next transaction will be a Read (R/W = 1)
or a Write (R/W = 0). If the address transmitted matches that
of any device on the bus, that device must respond with an
ACKNOWLEDGE (see Figure 8).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (see Figure 7), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (see Figure 9). To achieve this, data being written to
the ISL98002 is latched on a delayed version of the rising
edge of SCL. SCL is delayed and deglitched inside the
ISL98002 for three crystal clock periods (120ns for a 25MHz
crystal) to eliminate spurious clock pulses that could disrupt
serial communication.
When the contents of the ISL98002 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 10 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 11 shows two views of the steps necessary to read
one or more words from the Configuration Register.
ISL98002
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