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參數(shù)資料
| 型號： | ISL97702IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Boost with Dual Reference Outputs |
| 中文描述： | 1.2 A SWITCHING REGULATOR, 1100 kHz SWITCHING FREQ-MAX, DSO10 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, MO-229, DFN-10 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 489K |
| 代理商： | ISL97702IRZ |
9
FN7462.0
October 13, 2005
Fault Control
The input voltage at VDD, current in the VDDOUT switch,
voltage at V
OUT
and junction temperature Tj are
continuously monitored and can either restart the start-up
sequence or in some cases disable the ISL97702 boost
function as long as the fault is present.
Maximum Duty Cycle – LX
The maximum duty cycle Dmax, at which the power FET can
operate defines the upper limit of the regulator output to
input voltage ratio according to the formula: V
OUT
/V
IN
= 1/
(1-Dmax). In the ISL97702, Dmax is defined from the
minimum off-time toff(LX)min and the switching frequency.
If NSYNC is tied to VDD the internal oscillator defines Dmax
to:
Dmax(fosc) = 1 - toff(LX)min*fosc
With external synchronization at pin NSYNC
Dmax(NSYNC) = 1 - toff(LX)min*f(NSYNC)
The duty cycle at LX can be 0% (
pulse skipping
), if the
output voltage exceeds the target voltage set with the
feedback resistors.
Internal Schottky Diode – LX, V
OUT
The inductor node LX internally connects to the power FET
and to the anode of the integrated power Schottky diode.
The cathode of the diode is pin V
OUT
. An overvoltage
detector at V
OUT
continuously monitors the cathode voltage
and immediately disables the boost regulator if the voltage
exceeds the maximum allowable voltage.
Feedback Input Pins – FB0, FB1
Each feedback pin is either configured as feedback input pin
or as ground reference output pin for the external feedback
resistor chain. Configured as output the feedback pin is
switched to the internal reference ground via a low Ron MOS
transistor to achieve maximum accuracy of the regulated
output voltage. A current limit at FB0 and FB1 prevents
overloading in a fault condition.
External Synchronization Pin - NSYNC
Pin NSYNC can be used to synchronize the LX output pin with
an external clock signal in the range from 600kHz to 1.4MHz.
A frequency detector monitoring NSYNC enables external
synchronization if f(NSYNC) is higher than about 300kHz. If
the pin is e.g. static high the internal oscillator defines the LX
output frequency and phase. When externally synchronized
all falling edges at LX are timed from the falling edge of the
clock signal applied at NSYNC. The timing of the rising edge
at LX is defined by the boost controller.
TABLE 1. FAULT PROTECTION
FAULT
DESCRIPTION
FAULT
CONDITION
ISL97702 FAULT
REACTION
Undervoltage at
VDD
V(VDD) <
V(VDD)off
Disables I/Os and waits until
V(VDD) reaches V(VDD)on
to begin with the start-up
sequence
Overcurrent drawn
from VDDOUT
I(VDDOUT) >
It(VDDOUT)err
Disables VDDOUT switch
and LX driver and
immediately restarts the
start-up sequence
Overvoltage at
VOUT
V(VOUT) >
Vt(VOUT)err
Disables VDDOUT switch
and LX driver and waits until
output voltage V(VOUT)
drops to Vt(VOUT) to restart
the start-up sequence
Over Temperature
on chip
Tj > Toff
Disables VDDOUT switch
and LX driver and waits until
junction temp drops to “Ton”
to restart the start-up
sequence
FIGURE 16.
TABLE 2. PIN FEEDBACK CONFIGURATION DEPENDENT
ON SEL
SEL
FB0
FB1
0
Feedback Input
Ground Reference Output
1
Ground Reference Output
Feedback Input
ISL97702
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