參數(shù)資料
型號: ISL97653AIRZ
廠商: INTERSIL CORP
元件分類: 顯示驅(qū)動器
英文描述: 5-Channel Integrated LCD Supply
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PQCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, PLASTIC, QFN-40
文件頁數(shù): 17/18頁
文件大小: 523K
代理商: ISL97653AIRZ
17
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6367.0
December 6, 2007
When EN is taken high, voltage of pin PROT and V
OFF
start
ramping down. Once the PROT voltage falls below 0.9V,
A
VDD
starts up with a 9ms fixed soft-start time. Please note if
V
OFF
is to start earlier than
A
VDD
, then the SUPN needs to
connect to Vin, and Vin voltage should be larger than V
OFF
absolute value. The delay between V
OFF
and
A
VDD
can be
controlled by C30 in the typical application diagram and is
given by Equation 23:
The successful completion of the A
VDD
soft-start cycle
triggers two simultaneous events. V
ON
begins to ramp up
and the voltage on CDEL starts ramping up. When the
voltage reaches 1.215V, V
ON
slice starts.
Temperature Sensor
The ISL97653A also includes a temperature output for use
in system thermal management control. The integrated
sensor measures the die temperature over the -40°C to
+150°C range. Output is in the form of an analog voltage on
the TEMP pin in the range of 0V to 3V,
which is proportional
to the sensed die temperature. Temperature accuracy is
±8.5°C over the -40°C to +150°C temperature range.
The device should be disabled by the user when the TEMP
pin output reaches 3V ( = +150°C die junction). Operation of
the device between +125°C and +150°C can be tolerated for
short periods, however in order to maximize the life of the IC,
it is recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
Fault Sequencing
The ISL97653A has advanced overall fault detection
systems including Over Current Protection (OCP) for both
boost and buck converters, Under Voltage Lockout
Protection (UVLP) and Over-Temperature Protection.
Once the peak current flowing through the switching
MOSFET of the boost and buck converters triggers the
current limit threshold, the PWM comparator will disable the
output, cycle by cycle, until the current is back to normal.
Layout Recommendation
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place V
REF
and V
L
bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew
rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
T
DELAY
V
IN
0.9V
(
)
C
30
×
50
μ
A
(
)
=
(EQ. 23)
V
IN
VREF
V
LOGIC
EN
A
VDD
V
ON
V
OFF
V
ON
Slice
* For demonstration only, not to scale
PROT
CDEL
2.8V
0.9V
1.215V
FIGURE 18.
ISL97653A
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