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參數(shù)資料
| 型號： | ISL95311UIU10Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Terminal Voltage 0V to 13.2V, 128 Taps I2C Interface |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO10 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 192K |
| 代理商： | ISL95311UIU10Z |
4
FN8084.0
May 6, 2005
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
I
CC1
V
CC
supply current, volatile write/read f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read, and volatile write states only)
1
mA
I
CC2
V
CC
supply current, nonvolatile write
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
nonvolatile write states only)
3
mA
I
SB
V
CC
current, standby
V
CC
= +5.5V, I
2
C interface in standby state
V
CC
= +3.6V, I
2
C interface in standby state
5
μA
2
μA
I
V+
V+ bias current
V+ = 13.2V, V
CC
= +5.5V
1
μA
I
LkgDig
Leakage current, at pins SDA, SCL,
A0, and A1 pins
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 13)
DCP wiper response time
SCL falling edge of last bit of DCP data byte to
wiper change
1
μs
Vpor
(Note 13)
Power-on recall voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
VccRamp
(Note 10)
V
CC
ramp rate
0.2
V/ms
t
D
(Note 13)
Power-up delay
V
CC
above Vpor, to DCP initial value register
recall completed, and I
2
C Interface in standby
state
3
ms
EEPROM SPECS
EEPROM endurance
200,000
Cycles
EEPROM retention
Temperature
≤
75°C
50
Years
SERIAL INTERFACE SPECS
V
IL
A0, A1, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*
V
CC
V
V
IH
A0, A1, SDA, and SCL input buffer
HIGH voltage
0.7*
V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL input buffer hysteresis
0.05*
V
CC
V
V
OL
SDA output buffer LOW voltage,
sinking 4mA
0
0.4
V
Cpin
A0, A1, SDA, and SCL pin
capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window
900
ns
t
BUF
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
600
ns
ISL95311
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