參數(shù)資料
型號(hào)： ISL95311
廠商： Intersil Corporation
英文描述： Terminal Voltage 0V to 13.2V, 128 Taps I2C Interface
中文描述： 終端電壓為0V到13.2V，128絲錐I2C接口
文件頁(yè)數(shù)： 4/11頁(yè)
文件大?。?/td> 192K
代理商： ISL95311
4
FN8084.0
May 6, 2005
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
I
CC1
V
CC
supply current, volatile write/read f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read, and volatile write states only)
1
mA
I
CC2
V
CC
supply current, nonvolatile write
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
nonvolatile write states only)
3
mA
I
SB
V
CC
current, standby
V
CC
= +5.5V, I
2
C interface in standby state
V
CC
= +3.6V, I
2
C interface in standby state
5
μA
2
μA
I
V+
V+ bias current
V+ = 13.2V, V
CC
= +5.5V
1
μA
I
LkgDig
Leakage current, at pins SDA, SCL,
A0, and A1 pins
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 13)
DCP wiper response time
SCL falling edge of last bit of DCP data byte to
wiper change
1
μs
Vpor
(Note 13)
Power-on recall voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
VccRamp
(Note 10)
V
CC
ramp rate
0.2
V/ms
t
D
(Note 13)
Power-up delay
V
CC
above Vpor, to DCP initial value register
recall completed, and I
2
C Interface in standby
state
3
ms
EEPROM SPECS
EEPROM endurance
200,000
Cycles
EEPROM retention
Temperature
≤
75°C
50
Years
SERIAL INTERFACE SPECS
V
IL
A0, A1, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*
V
CC
V
V
IH
A0, A1, SDA, and SCL input buffer
HIGH voltage
0.7*
V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL input buffer hysteresis
0.05*
V
CC
V
V
OL
SDA output buffer LOW voltage,
sinking 4mA
0
0.4
V
Cpin
A0, A1, SDA, and SCL pin
capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window
900
ns
t
BUF
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
600
ns
ISL95311
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ISL95311WIU10Z Terminal Voltage 0V to 13.2V, 128 Taps I2C Interface
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ISL95311UIU10Z 功能描述:IC XDCP 128-TAP 50KOHM 10-MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類(lèi)型:易失 接口:6 線(xiàn)串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR)
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