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參數(shù)資料
| 型號： | ISL9217IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 8 to 12 Cell Li-Ion Battery Overcurrent Protection and Analog Front End Chip Set |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-24 |
| 文件頁數(shù)： | 27/33頁 |
| 文件大?。?/td> | 645K |
| 代理商： | ISL9217IRZ |
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27
FN6488.1
November 2, 2007
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
After receiving the acknowledge after the data byte, the device
automatically increments the address. So, before sending the
stop bit, the master may send additional data to the device
without re-sending the slave and address bytes. After writing to
address 0AH, the address “wraps around’ to address 0.
Read Operations
Read operations are initiated in the same manner as write
operations with the host sending the address where the read
is to start (but no data). Then, the host sends an ACK, a
repeated start and the slave byte with the LSB = 1. After the
device acknowledges the slave byte, the device sends out
one bit of data for each master clock. After the slave sends 8
bits to the master, the master sends a NACK (Not
acknowledge) to the device to indicate that the data transfer
is complete, then the master sends a stop bit. See Figure 13.
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer.
Therefore, the master, instead of sending a NACK and the
stop bit, can send additional clocks to read the contents of
the next register - without sending another slave and
address byte.
If the last address read or written is known, the master can
initiate a current address read. In this case, only the slave byte
is sent before data is returned. See Figure 13.
Cascade Operation
When devices are cascaded, the lower device has the I
2
C
slave address of 0101 000x and the upper device has the
address 0101 001x (See Figure 14), but the operation of
cascaded devices is transparent to the microcontroller
master device.
The serial interface between cascaded ISL9216 and
ISL9217 devices has one clock and two data lines. There is
also a high voltage reference for this commication link. See
Figure 15. The interface lines are:
SCLHV, which is a level shifted clock from the lower
device (ISL9216) to the upper device (ISL9217);
SDAOHV and SDAO, which send level shifted data out of
the ISL9216 and ISL9217 (respectively); and
SDAIHV and SDAI, which are level shifted inputs into the
ISL9216 and ISL9217 (respectively).
HVI2C (ISL9216), which is a reference voltage for the level
shifted interface. This connects to the ISL9217 RGO pin.
0
0 1 0 1
0 x
0
S
T
A
R
T
S
T
O
P
SLAVE
BYTE
REGISTER
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
SDA BUS
S
F
S
S
F
M
FIGURE 12. WRITE SEQUENCE
ISL9216: x = 0 [SLAVE BYTE = 50H]
ISL9217: x = 1 [SLAVE BYTE = 52H]
FIGURE 13. READ SEQUENCE
1
0 1 0 1
0 0
0
S
T
A
R
T
S
T
O
P
SLAVE
BYTE
DATA
A
C
K
N
A
C
K
ISL9208: SLAVE BYTE = 010100xH
0
0 1 0 1
0 0
0
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
A
C
K
A
C
K
SDA BUS
S
F
S
S
F
M
1
0 1 0 1
0 0
0
S
T
A
R
T
S
T
O
P
SLAVE
BYTE
DATA
A
C
K
N
A
C
K
RANDOM READ
CURRENT ADDRESS READ
0
1
0
1
0
0
0
X
ISL9216 SLAVE BYTE
ISL9217 SLAVE BYTE
0
1
0
1
0
0
1
X
FIGURE 14. DEVICE SLAVE BYTES
ISL9216
ISL9217
SDA
SCL
1010 001x
I
2
C
BLOCK
SCL
SCLHV
SDAI
FIGURE 15. I
2
C CASCADED INTERFACE
1010 000x
SDAOHV
HVI2C
SDAO
SDAIHV
LEVEL
SHIFT
I
2
C
BLOCK
LEVEL
SHIFT
LEVEL
SHIFT
RGO
ISL9216, ISL9217
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