參數(shù)資料
型號: ISL9206DRZ-T
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: FlexiHash+ For Battery Authentication
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: ROHS COMPLIANT, PLASTIC, TDFN-8
文件頁數(shù): 9/17頁
文件大小: 341K
代理商: ISL9206DRZ-T
9
FN9260.2
January 5, 2007
TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING
PARAMETER
SYM
DESCRIPTION
MIN
TYP
MAX
UNIT
Bit Time
BT
H
x = 0.5, 1, 2, or 4
173.6/x
μ
s
Deglitch period
tg
PW (Pulse Width) less than this will result in a frame error
0.124
BT
H
‘1’ pulse width
t1
H
PW in this range will be interpreted as a ‘1’ code
0.227
0.453
BT
H
‘0’ pulse width
t0
H
PW in this range will be interpreted as a ‘0’ code
0.591
0.824
BT
H
‘break’ time
tb
H
PW in this range will be interpreted as a ‘break’ command
1
100
BT
H
NOTE: Unless otherwise stated, all pulse width (PW) referenced are with respect to an active-low pulse.
TABLE 3. DEVICE TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING
PARAMETER
SYM
DESCRIPTION
MIN
TYP
MAX
UNIT
Bit Time
BT
D
x = 0.5, 1, 2, or 4
164.2/x
172.8/x
181.4/x
μ
s
‘1’ pulse width
t1
D
‘1’ code transmit pulse width
0.304
BT
D
‘0’ pulse width
t0
D
‘0’ code transmit pulse width
0.696
BT
D
‘break’ time
tb
D
PW in this range will be interpreted as a ‘break’ command
1.391
BT
D
FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS
V
DDD
V
DDH
R
PU
TX
RX
TX
RX
HOST
DEVICE
Open-Drain
Port Pin
1.5
μ
A
ESD
Diode
ESD
Diode
6pF
FIGURE 8. THE BUS SIGNAL TIMING DIAGRAM
glitch
t1
t0
tb
tg
XSD
1
0
Break
BT
ISL9206
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