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參數(shù)資料
| 型號： | ISL9206 |
| 廠商： | Intersil Corporation |
| 英文描述： | FlexiHash+ For Battery Authentication |
| 中文描述： | FlexiHash對于電池認證 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISL9206 |
14
FN9260.2
January 5, 2007
ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET
SET #2 (SE2A/B/C/D)
These address locations store the second set of secrets to
be used for hash calculation. Reading and writing to this
register can be disabled by setting the SLO[1] bit at OTP
ROM location 0-00[1].
ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET
SET #3 (SE3A/B/C/D)
These address locations store the optional third set of
secrets to be used for hash calculation. Reading and writing
to this register can be disabled by setting the SLO[0] bit at
OTP ROM location 0-00[0].
Alternately, this memory space can be used to store
additional cell information which can be accessed by the
host. In this case, the SLO[0] bit should not be set.
TABLE 14. MASTER CONTROL REGISTER (MSCR)
BIT
NAME
TYPE
DEFAULT
DESCRIPTION
7
eEEW
R
0
<1/0>
OTP ROM Write-in-Progress Interrupt Enable: When enabled, it allows the sEEW bit to flag an
interrupt whenever the sEEW bit is set by its interrupt event. The eEEW bit is fixed at ‘1’ when none
of the OTP ROM lock-out bits is set. When any or both of the lock-out bits are set, the eEEW bit
will become permanently ‘0’ after a reset.
6
eINT
RW
0
<1>
Global Interrupt Enable: When enabled, it allows the sBER or sACC bit to flag an interrupt to the
host whenever any of the respective interrupt event occurred.
(Default setting loaded from OTP ROM location 0-00[3])
5:2
--
R
0
Unused.
1
ASLP
RW
0
<1>
Auto Sleep Mode enable: When set, the ISL9206 will automatically enter Sleep mode after about
1s of XSD bus inactivity. When cleared, the device can only enter Sleep mode on Opcode
command.
(Default setting loaded from OTP ROM location 0-00[2])
0
SRST
WC
0
Soft Reset: When a ‘1’ is written, and all registers are reset to their default states, all bus counters
and timers are reset to their start-up conditions, and device configuration information is reloaded
from OTP ROM. After the reset sequence is completed, a ‘break’ pulse is sent to the host.
TABLE 15. DEVICE STATUS REGISTER (STAT)
BIT
NAME
TYPE
DEFAULT
DESCRIPTION
7
sEEW
RC
0
OTP ROM Write-in-Progress Flag: This bit is set when attempt is made by the host to read from
or write to the ISL9206 while the ROM is still processing the previous write instruction.
6
sBER
RC
0
XSD Bus Error Flag: This bit is set when one or more of the following occurred at the bus interface:
a) An invalid pulse width is received
b) Bus activity is detected before the device completes its power-up sequence
c) An invalid BYTES field in the instruction frame
d) Improper authentication sequence is detected
e) Reading secret information after the corresponding lock-out bits are set
5
sACC
RC
0
Register Access Error Flag: This bit is set whenever an instruction frame attempts to access a
protected register as follows:
a) Writing to OTP ROM after the ISL9206 has been locked out (any or both of the lock-out bits set)
b) Accessing the ISL9206ís Test and Trim Registers when the device is not in test mode
4
--
R
0
Unused
3:2
DAB[1:0]
R
00
<00>
Device Address Bit Setting:
Loaded from OTP ROM location 0-00[7:6] during power-up.
1:0
SLO[1:0]
R
00
<00>
Secrets Lock-out Bits Setting:
Loaded from OTP ROM location 0-00[1:0] during power-up.
ISL9206
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