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參數(shù)資料
| 型號(hào)： | ISL90843UIU1027Z-TK |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大小： | 0K |
| 描述： | IC XDCP 256-TAP 50OHM 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
8
FN8095.2
March 29, 2006
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90843
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 11). On power-up of the ISL90843 the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90843 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 11). A START condition is ignored during the power-
up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 11). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 12).
The ISL90843 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90843 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is in the Read/Write bit. Its value
is “1” for a Read operation, and “0” for a Write operation
(See Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
01
0
1
0
A1
A0
R/W
(MSB)
(LSB)
Logic values at pins A1, and A0 respectively
FIGURE 11. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
ISL90843
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