FN8094.1 February 8, 2006 Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid" />
參數(shù)資料
型號: ISL90841WIV1427Z-TK
廠商: Intersil
文件頁數(shù): 3/12頁
文件大?。?/td> 0K
描述: IC POT DGTL QUAD 10K OHM 14TSSOP
產(chǎn)品培訓(xùn)模塊: Digitally Controlled Potentiometers
標(biāo)準(zhǔn)包裝: 1
系列: XDCP™
接片: 256
電阻(歐姆): 10k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±45 ppm/°C
存儲器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ISL90841WIV1427Z-TKDKR
11
FN8094.1
February 8, 2006
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90841 responds with an ACK. At this time, the device
enters its standby state (See Figure 17).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90841 responds with an ACK. Then the ISL90841
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 18).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
ISL90841
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