參數(shù)資料
型號: ISL9012IRBJZ
廠商: INTERSIL CORP
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual LDO with Low Noise, Low IQ, and High PSRR
中文描述: DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10
封裝: 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-229WEED-3, DFN-10
文件頁數(shù): 9/11頁
文件大小: 300K
代理商: ISL9012IRBJZ
9
FN9220.0
September 27, 2005
Block Diagram
Functional Description
The ISL9012 contains all circuitry required to implement two
high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9012 adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device turn-
on time.
Power Control
The ISL9012 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1
μ
A.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power up.
If EN1 is brought high, and EN2 is goes high before the VO1
output stablizes, the ISL9012 delays the VO2 turn-on until
the VO1 output reaches its target level. This minimizes input
current surge due to concurrent turn-on.
LDO
ERROR
AMPLIFIER
IS2
1V
QEN2
LDO-2
LDO-1
POR
COMPARATOR
VOK2
POR
VREF
TRIM
VIN
VO1
VO2
POR
CPOR
CBYP
GND
EN2
EN1
CONTROL
LOGIC
POR
DELAY
VOLTAGE
REFERENCE
GENERATOR
BANDGAP AND
TEMPERATURE
SENSOR
UVLO
VOK2
1.00V
0.94V
0.90V
I
I
Q
Q
VO2
~1.0V
ISL9012
相關(guān)PDF資料
PDF描述
ISL9012IRBJZ-T Dual LDO with Low Noise, Low IQ, and High PSRR
ISL9012IRFJZ Dual LDO with Low Noise, Low IQ, and High PSRR
ISL9012IRFJZ-T Dual LDO with Low Noise, Low IQ, and High PSRR
ISL9012IRGCZ Dual LDO with Low Noise, Low IQ, and High PSRR
ISL9012IRGCZ-T Dual LDO with Low Noise, Low IQ, and High PSRR
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