參數(shù)資料
| 型號： | ISL76321ARZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO SERDES LONG 16BIT 48QFN |
| 標準包裝： | 260 |
| 功能： | 串行器/解串器 |
| 輸入類型： | RGB |
| 輸出類型： | 串行 |
| 輸入數(shù)： | 16 |
| 輸出數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 管件 |
ISL76321
10
FN7803.1
December 23, 2013
Applications
Detailed Description and Operation
A pair of ISL76321 SERDES transports 16-bit parallel video for
the ISL76321 along with auxiliary data over a single 100
Ω
differential cable either to a display or from a camera. Auxiliary
data is transferred in both directions every video frame. This
feature can be used for remote configuration and telemetry.
The benefits include lower EMI, lower costs, greater reliability and
space savings. The same device can be configured to be either a
serializer or deserializer by setting one pin (VIDEO_TX),
simplifying inventory. RGBA/C, VSYNC, HSYNC, and DATAEN pins
are inputs in serializer mode and outputs in deserializer mode.
The video data presented to the serializer on the parallel LVCMOS
bus is serialized into a high-speed differential signal. This
differential signal is converted back to parallel video at the
remote end by the deserializer. The Side Channel data (auxiliary
data) is transferred between the SERDES pair during the first two
lines of the vertical video blanking interval.
When the side-channel is enabled, which is the default, there will
be a number of PCLK cycles uncertainty from frame-to-frame.
This should not cause sync problems with most displays, as this
occurs during the vertical front porch of the blanking period.
When properly configured, the SERDES link supports end-to-end
transport with fewer than one error in 1010 bits.
Differential Signals and Termination
The ISL76321 serializes the 16-bit parallel data plus 3 sync
signals at 20x the PCLK_IN frequency. The extra 2 bits per word
come from the 8b/10b encoding scheme which helps create the
highest quality serial link.
The high bit rate of the differential serial data requires special
care in the layout of traces on PCBs, in the choice and assembly
of connectors, and in the cables themselves.
PCB traces need to be adjacent, matched in length and drawn to
result in a differential 100 controlled impedance. For best EMI
performance, the cable should be low loss and have a differential
100 impedance. The maximum cable length for a functioning
link is dependent on the PCLK_IN frequency, the cable loss and
impedance, as well as the pre-emphasis and equalization
settings. Functioning links of 25 meters are often possible at the
maximum frequency.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode voltage
difference and local power supply variations between two
SERDES. The serializer outputs DC balanced 8b/10b line code,
which allows AC-coupling.
The AC-coupling capacitor on SERIO pins must be 27nF on the
serializer board and 27nF on the deserializer board. The value of
the AC-coupling capacitor is very critical since a value too small
will attenuate the high-speed signal at a low clock rate. A value
too big will slow down the turn around time for the side-channel.
It is an advantage to have the pair of capacitors as closely
matched as possible.
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into PCLK_IN
pin. REF_CLK is used to recover the clock from the high-speed
serial stream. REF_CLK is very sensitive to any instability. The
following conditions must be met at all times after power is
applied to the deserializer, or else the deserializer may need a
manual reset:
VDD must be applied and stable
REF_CLK frequency must be within the limits specified
REF_CLK amplitude must be stable
A simple 3.3V CMOS crystal oscillator can be used for REF_CLK
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at all times,
including during power-up and power-down. To meet this
requirement, the 3.3V supply must be powered up before the
1.8V supply.
For the deserializer, REF_CLK must not be applied before the
device is fully powered up. Applying REF_CLK before power-up
FIGURE 4. PARALLEL VIDEO OUTPUT TIMING
DESERIALIZER MODE
PCLK_OUT
(RISING EDGE
DEFAULT)
1/FOUT
tODC
tOR
tOF
tDV
VALID DATA
PREVIOUS DATA HELD
RGBA[7:0],
RGBC[7:0]
HSYNC OR VSYNC
( HVSYNCPOL = ‘0’)
DATAEN
(ACTIVE ‘1’ DEFAULT)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL76321ARZ-T13 | 功能描述:串行器/解串器 - Serdes ISL76321 48L 7X7(PUN CHED AUTO RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| ISL76321ARZ-TK | 功能描述:串行器/解串器 - Serdes ISL76321 48L 7X7(PUN CHED 1K AUTO RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| ISL76322 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16-Bit Long-Reach Video Automotive Grade SERDES |
| ISL76322_1108 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16-Bit Long-Reach Video Automotive Grade SERDES |
| ISL76322ARZ | 功能描述:串行器/解串器 - Serdes ISL76322 48L 7X7(PUN CHED AUTO RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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