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參數(shù)資料
| 型號： | ISL6613B |
| 廠商： | Intersil Corporation |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP |
| 中文描述： | 先進(jìn)的同步整流降壓MOSFET驅(qū)動(dòng)器與前葡萄牙過壓保護(hù) |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 302K |
| 代理商： | ISL6613B |
8
FN9205.3
July 27, 2006
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 6.9V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 5.6V (typically), operation of the driver is
disabled.
Pre-POR Overvoltage Protection
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits during initial startup. The PHASE is
connected to the gate of the low side MOSFET (LGATE),
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial start-up. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
When VCC drops below its POR level, both gates pull low
and the Pre-POR overvoltage protection circuits are not
activated until VCC resets.
Internal Bootstrap Device
Both drivers feature an internal bootstrap schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above UVCC + 5V and its capacitance value can be
chosen from the following equation:
where Q
G1
is the amount of gate charge per upper MOSFET
at V
GS1
gate-source voltage and N
Q1
is the number of
control MOSFETs. The
V
BOOT_CAP
term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q
G
, from the data
sheet is 10nC at 4.5V (V
GS
) gate-source voltage. Then the
Q
GATE
is calculated to be 53nC for UVCC (i.e. PVCC in
ISL6613B, VCC in ISL6612B) =12V. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.267
μ
F is required.
Gate Drive Voltage Versatility
The ISL6612B and ISL6613B provide the user flexibility in
choosing the gate drive voltage for efficiency optimization.
The ISL6612B upper gate drive can be driven above VCC
rising POR (7V) to 12V, but the lower drive rail can range
from 12V down to 5V depending on what voltage is applied
to PVCC. The ISL6613B ties the upper and lower drive rails
together. Simply applying a voltage from 5V up to 12V on
PVCC sets both gate drive rail voltages simultaneously.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
SW
), the output drive impedance, the
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room temperature,
while the power dissipation capacity in the EPSOIC and DFN
packages, with an exposed heat escape pad, is more than
2W and 1.5W, respectively. Both EPSOIC and DFN
packages are more suitable for high frequency applications.
See Layout Considerations paragraph for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
C
BOOT_CAP
Q
BOOT_CAP
-------------------------------------
≥
Q
GATE
Q
-----------------------------------
UVCC
GS1
N
Q1
=
(EQ. 1)
50nC
20nC
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
V
BOOT_CAP
(V)
C
B
(
μ
F
1.6
1.4
1.2
1.
0.8
0.6
0.4
0.2
0.0
0.3
0.0
0.1
0.2
0.4
0.5
0.6
0.9
0.7
0.8
1.0
Q
GATE
= 100nC
ISL6612B, ISL6613B
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