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參數(shù)資料
| 型號： | ISL6610IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | MOSFETs |
| 英文描述： | Dual Synchronous Rectified MOSFET Drivers |
| 中文描述： | 4 A BUF OR INV BASED MOSFET DRIVER, PQCC16 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220VGGC, QFN-16 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 279K |
| 代理商： | ISL6610IRZ |
9
FN6395.0
November 22, 2006
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R
UGPH
) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C
GD
/C
GS
ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C
DS
/C
GS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20k
Ω
typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
following equations, which assume a fixed linear input ramp
and neglect the clamping effect of the body diode of the
upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10M
Ω
or greater) probe to
ensure a safe design margin.
V
GS_MILLER
-------
R C
rss
1
e
V
–
-------
R C
iss
---------------------------------
–
=
R
R
UGPH
R
GI
+
=
C
rss
C
GD
=
C
iss
C
GD
C
GS
+
=
(EQ. 5)
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
VIN
Q
UPPER
D
S
G
R
GI
R
U
BOOT
DU
C
DS
C
GS
C
GD
DL
PHASE
VCC
I
C
BOOT
UGATE
ISL6610, ISL6610A
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