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參數(shù)資料
| 型號(hào)： | ISL6609ACRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | MOSFETs |
| 英文描述： | 7-Bit Bus Interfaces With 3-State Outputs 20-SOIC 0 to 70 |
| 中文描述： | 4 A AND GATE BASED MOSFET DRIVER, PQCC8 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220VEEC, QFN-8 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 321K |
| 代理商： | ISL6609ACRZ-T |
7
FN9221.0
August 10, 2005
bootstrap resistor is designed to reduce the overcharging of
the bootstrap capacitor when exposed to excessively large
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
that use D
2
-PAK and D-PAK MOSFETs or excessive layout
parasitic inductance.
The following equation helps select a proper bootstrap
capacitor size:
where Q
G1
is the amount of gate charge per upper MOSFET
at V
GS1
gate-source voltage and N
Q1
is the number of
control MOSFETs. The
V
BOOT_CAP
term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q
G
, from the data
sheet is 10nC at 4.5V (V
GS
) gate-source voltage. Then the
Q
GATE
is calculated to be 22nC at VCC level. We will
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.110
μ
F is required. The next larger standard value
capacitance is 0.22μF. A good quality ceramic capacitor is
recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
SW
), the output drive impedance, the
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room temperature,
while the power dissipation capacity in the QFN package,
with an exposed heat escape pad, is slightly better. See
Layout Considerations paragraph for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively,
where the gate charge (Q
G1
and Q
G2
) is defined at a
particular gate to source voltage (V
GS1
and V
GS2
) in the
corresponding MOSFET datasheet; I
Q
is the driver’s total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are number of upper and lower MOSFETs,
respectively. The I
Q
V
CC
product is the quiescent power of
the driver without capacitive load and is typically negligible.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
G1
and R
G2
, should be a short to avoid
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R
GI1
and R
GI2
) of
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as:
C
BOOT_CAP
Q
BOOT_CAP
-------------------------------------
≥
Q
GATE
Q
-------------------------------
VCC
GS1
N
Q1
=
(EQ. 1)
50nC
20nC
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
V
BOOT
(V)
C
B
(
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.3
0.0
0.1
0.2
0.4
0.5
0.6
0.9
0.7
0.8
1.0
Q
GATE
= 100nC
1.8
2.0
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
Q
VCC
+
+
=
(EQ. 2)
P
Qg_Q1
Q
----------------------------------
VCC
2
GS1
F
SW
N
Q1
=
P
Qg_Q2
Q
----------------------------------
VCC
2
GS2
F
SW
N
Q2
=
I
DR
Q
-----------------------------------------------------
UVCC
GS1
N
Q
----------------------------------------------------
LVCC
GS2
N
+
F
SW
I
Q
+
=
(EQ. 3)
P
DR
P
DR_UP
P
DR_LOW
I
Q
VCC
+
+
=
(EQ. 4)
P
DR_UP
R
+
R
HI1
R
EXT1
--------------------------------------
R
+
R
LO1
R
EXT1
---------------------------------------
+
P
2
---------------------
=
P
DR_LOW
R
+
R
HI2
R
EXT2
--------------------------------------
R
+
R
LO2
R
EXT2
---------------------------------------
+
P
2
---------------------
=
R
EXT2
R
G1
R
N
Q1
-------------
+
=
R
EXT2
R
G2
R
N
Q2
-------------
+
=
ISL6609, ISL6609A
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