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參數(shù)資料
| 型號(hào)： | ISL6594DCRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | MOSFETs |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features |
| 中文描述： | 3 A HALF BRDG BASED MOSFET DRIVER, PDSO10 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 260K |
| 代理商： | ISL6594DCRZ-T |
5
FN9282.0
March 30, 2006
UGATE Fall Time (Note 4)
t
FU
V
PVCC
= 12V, 3nF Load, 90% to 10%
-
18
-
ns
LGATE Fall Time (Note 4)
t
FL
V
PVCC
= 12V, 3nF Load, 90% to 10%
-
12
-
ns
UGATE Turn-On Propagation Delay (Note 4)
t
PDHU
V
PVCC
= 12V, 3nF Load, Adaptive
-
10
-
ns
LGATE Turn-On Propagation Delay (Note 4)
t
PDHL
V
PVCC
= 12V, 3nF Load, Adaptive
-
10
-
ns
UGATE Turn-Off Propagation Delay (Note 4)
t
PDLU
V
PVCC
= 12V, 3nF Load
-
10
-
ns
LGATE Turn-Off Propagation Delay (Note 4)
t
PDLL
V
PVCC
= 12V, 3nF Load
-
10
-
ns
LG/UG Three-State Propagation Delay (Note 4)
t
PDTS
V
PVCC
= 12V, 3nF Load
-
10
-
ns
OUTPUT (Note 4)
Upper Drive Source Current
I
U_SOURCE
V
PVCC
= 12V, 3nF Load
-
1.25
-
A
Upper Drive Source Impedance
R
U_SOURCE
150mA Source Current
1.4
2.0
3.0
Ω
Upper Drive Sink Current
I
U_SINK
V
PVCC
= 12V, 3nF Load
-
2
-
A
Upper Drive Sink Impedance
R
U_SINK
150mA Sink Current
0.9
1.65
3.0
Ω
Lower Drive Source Current
I
L_SOURCE
V
PVCC
= 12V, 3nF Load
-
2
-
A
Lower Drive Source Impedance
R
L_SOURCE
150mA Source Current
0.85
1.3
2.2
Ω
Lower Drive Sink Current
I
L_SINK
V
PVCC
= 12V, 3nF Load
-
3
-
A
Lower Drive Sink Impedance
R
L_SINK
150mA Sink Current
0.60
0.94
1.35
Ω
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Functional Pin Description
PACKAGE PIN #
PIN
SYMBOL
FUNCTION
SOIC
DFN
1
1
UGATE
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under Description for guidance in choosing the capacitor value.
-
3, 8
N/C
No Connection.
3
4
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under Description for further details. Connect this pin to the PWM output of the
controller.
4
5
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5
6
LGATE
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6
7
VCC
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
7
9
PVCC
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
ISL6594D
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