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參數(shù)資料
| 型號(hào)： | ISL6594DCBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features |
| 中文描述： | 3 A HALF BRDG BASED MOSFET DRIVER, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 260K |
| 代理商： | ISL6594DCBZ |
8
FN9282.0
March 30, 2006
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
where the gate charge (Q
G1
and Q
G2
) is defined at a
particular gate to source voltage (V
GS1
and V
GS2
) in the
corresponding MOSFET datasheet; I
Q
is the driver’s total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are number of upper and lower MOSFETs,
respectively; PVCC is the drive voltage for both upper and
lower FETs. The I
Q*
VCC product is the quiescent power of
the driver without capacitive load and is typically 116mW at
300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
G1
and R
G2
) and the internal gate resistors
(R
GI1
and R
GI2
) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. Careful layout can help minimize such
unwanted stress. The following advice is meant to lead to an
optimized layout:
Keep decoupling loops (PVCC-GND and BOOT-PHASE)
as short as possible.
Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, GND,
PVCC) should be short and wide, as much as possible.
Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
In addition, for heat spreading, place copper underneath the
IC whether it has an exposed pad or not. The copper area
can be extended beyond the bottom area of the IC and/or
connected to buried power ground plane(s) with thermal
vias. This combination of vias for vertical heat escape,
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
Q
VCC
+
+
=
(EQ. 2)
P
Qg_Q1
Q
--------------------------------------
PVCC
2
GS1
F
SW
N
Q1
=
P
Qg_Q2
Q
--------------------------------------
PVCC
2
GS2
F
SW
N
Q2
=
I
DR
Q
-----------------------------------------------------
PVCC
V
GS1
Q
-----------------------------------------------------
PVCC
V
GS2
+
F
SW
I
Q
+
=
(EQ. 3)
P
DR
P
DR_UP
P
DR_LOW
I
Q
VCC
+
+
=
(EQ. 4)
P
DR_UP
R
+
R
HI1
R
EXT1
--------------------------------------
R
+
R
LO1
R
EXT1
---------------------------------------
+
P
---------------------
=
P
DR_LOW
R
HI2
R
EXT2
---------------+
R
LO2
R
EXT2
-----------------+
+
P
---------------------
=
R
EXT1
R
G1
R
Q1
-------------
+
=
R
EXT2
R
G2
R
Q2
-------------
+
=
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q1
D
S
G
R
GI1
R
G1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
PVCC
PVCC
Q2
D
S
G
R
GI2
R
G2
R
HI2
C
DS
C
GS
C
GD
R
LO2
ISL6594D
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