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參數(shù)資料
| 型號(hào)： | ISL6594D |
| 廠商： | Intersil Corporation |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features |
| 中文描述： | 先進(jìn)的同步整流降壓MOSFET驅(qū)動(dòng)器的保護(hù)功能 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大小： | 260K |
| 代理商： | ISL6594D |
9
FN9282.0
March 30, 2006
extended copper plane, and buried planes for heat
spreading allows the IC to achieve its full thermal potential.
Upper MOSFET Self Turn-On Effects At Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, because of
self-coupling via the internal C
GD
of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R
UGPH
) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C
GD
/C
GS
ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C
DS
/C
GS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, a 5k
to 10k
Ω
resistor is typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
following equations, which assume a fixed linear input ramp
and neglect the clamping effect of the body diode of the
upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10M
Ω
or greater) probe to
ensure a safe design margin.
V
GS_MILLER
dt
-------
R C
rss
1
e
V
–
-------
R C
iss
---------------------------------
–
=
R
R
UGPH
R
GI
+
=
C
rss
C
GD
=
C
iss
C
GD
C
GS
+
=
(EQ. 5)
FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
VIN
Q
UPPER
D
S
G
R
GI
R
U
BOOT
DU
C
DS
C
GS
C
GD
DL
PHASE
PVCC
I
C
BOOT
UGATE
ISL6594D
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