參數(shù)資料
型號(hào)： ISL6592DNZ-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： FUSE, ANTISURGE 2A
中文描述： SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PQFP48
封裝： 7 X 7 MM, ROHS COMPLIANT, LASTIC, MS-026-BBC, LQFP-48
文件頁(yè)數(shù)： 9/21頁(yè)
文件大?。?/td> 378K
代理商： ISL6592DNZ-T
9
FN9163.1
August 5, 2005
30
ISEN1
I
Analog
Phase channel #1 ADC current sense input. This pin is held at a
virtual ground, with programmable offset from 25 to 300mV. An
external sense resistor is connected to the drain of the low side FET
so that its current may be determined. The current sourced from the
input is given by: ISEN = (Voffset - VRDSON)/RSEN1. Input current
is digitized with the ADC with an effective ADC range of 0 -275μA in
4.3μA steps.
31
ISEN2
I
Analog
Phase channel #2 ADC current sense input. See ISEN1 for
description.
32
ISEN3
I
Analog
Phase channel #3 ADC current sense input. See ISEN1 for
description.
33
ISEN4
I
Analog
Phase channel #4 ADC current sense input. See ISEN1 for
description.
34
ISEN5
I
Analog
Phase channel #5 ADC current sense input. See ISEN1 for
description.
35
ISEN6
I
Analog
Phase channel #6 ADC current sense input. See ISEN1 for
description.
36
VDD
I
VDD
3.3V power supply connection
37
RESET_N
I
3.3V CMOS
Active low asynchronous system reset to place ISL6592 into default
state
“1”
asynchronous reset disabled
“0”
asynchronous reset enabled
38
CAL_CUR_SEN
I
Analog
Calibration current sense input. Measures the voltage across the
sense resistor. FET gate voltage is adjusted via an opamp loop such
that the voltage across the resistor is set at 100mV.
39
CAL_CUR_EN
O
Analog
Calibration current enable output. Drives the calibration FET gate
voltage to adjust its r
DS(ON)
such that voltage across the sense
resistor is set at 100 mV.
40
FAULT1
O
3.3V CMOS
Programmable fault indicator #1
41
FAULT2
O
3.3V CMOS
Programmable fault indicator #2
42
TCLK_SEL
I
3.3V CMOS
Tie to Ground for normal operation
43
SADDR
I
3.3V CMOS
I
2
C address LSB select
“1”
1110001 selected
“0”
1110000 selected
44
SDA
I
3.3V CMOS
I
2
C interface serial data line.
45
SCL
I
3.3V CMOS
I
2
C interface serial clock line.
46
LL0
I
1.2V CMOS
Processor load line select input control signal (MSB). Selects
regulator load line resistance.
47
LL1
I
1.2V CMOS
Processor load line select input control signal (LSB). Selects
regulator load line resistance.
48
VD25
I
Analog
Decoupling capacitor for 2.5V internally generated voltage
0.01μF recommended, 0.1μF max
Pin Description
(Continued)
PIN #
NAME
I/O
TYPE
DESCRIPTION
ISL6592
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