參數(shù)資料
型號(hào)： ISL6590DR
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： Dual Low-Noise Wide-Bandwidth Precision Amplifier 8-PDIP -40 to 85
中文描述： SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC64
封裝： 9 X 9 MM, PLASTIC, QFN-64
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 1525K
代理商： ISL6590DR
10
PID
Feedback Control PID block not only performs each of the
basic Proportional, Integral, and Differential compensation
components, it also includes a Low Pass Filter (LPF) to help
reduce high frequency noise and a transient recovery path to
help transient event. The coefficients used in the PID portion
are Kp, Kd, and Ki. The coefficients used in the LPF are Kfp
and Kfd.
The calculations in the transient path take the differential
AVP output (DAVPout), gained up by Kdf, and then added to
the integral path accumulator. The input to the Low pass
filter is the adjusted Verr by AVP output. The coefficients for
the PID block are stored in modifiable registers in the
Controller Memory Map. In order to put a cap on PID output,
the Duty_limit term from the memory map is used to saturate
the output of the PID block.
Current Balancing
This block adjusts each individual channel current, I
1-6
, by
comparing it with the average current, I
AV
, of all the active
channels. The difference between each channel current and
the average current passes through a low pass filter and a
shift operation to suppress it before it is added to PID output.
I
ERR
is an input from the Current Sharing block (not
implemented) and represents a difference between the local
module’s average current and the average currents of all
other modules in the system.
PWM Generator
The PWM generator delivers 1-6 complementary high side
(PWM) and low side (NDRIVE) outputs to each of the
ISL6580 power stage’s inputs. A high state on the PWM
signal enables the high side integrated P-channel MOSFET
of each ISL6580. The low side drive signal is a
complementary, non-overlapped version of the PWM signal.
The rising edge of each PWM phase is evenly distributed
over the switching period. Prior to each PWM output, the
generator samples the PID output value and generates a
pulse that is proportional to the sampled value.
A high level on the OUTEN input signal enables the PWM
generator. The PWRGD output signal denotes that the
output is regulated within the specified limits. If OUTEN is
low or a major fault occurs, PWRGD will be low.
Asynchronous Serial Interface Details
Writes to the control registers from the ASI are second
priority to the fault and state monitoring writes to the control
registers. The priority is handled by the Memory Bus
Multiplexer. The ASI functions at 115.2 kbits/second with a
50ms inter-byte time-out and reset. The ASI waits for
command bytes after reset. The serial data is constructed
with a start bit, eight data bits, and a stop bit. Parity is not
supported.
Controller specific serial interface commands are restricted
to reads and writes of the controller memory map. Details
are provided in Tables 2-5.
EEPROM Operation
After the Controller powers up, the SPI Serial EEPROM
interface is polled to see if a memory device is connected.
This polling is performed by doing a SPI Memory Write
Enable (WREN) command and then doing a Read Status
Register (RDSR) to see if the Write Enable bit is set
correctly. If an external SPI Serial EEPROM is connected to
the controller, the Non-Volatile Memory block asserts an
EXTMEM bit in the Memory Status Register. If the
NVMEMCODE check passes, all non-volatile memory
locations in the Controller Memory Map are read from the
serial memory and loaded into the local register copies in the
Controller. Once the startup checks and configuration
loading (if possible) are complete, SPI_READY bit is set in
TABLE 2. ASYNCHRONOUS SERIAL INTERFACE
CONTROLLER SPECIFIC COMMANDS
COMMAND
NAME
CODE
(8 BITS)
DESCRIPTION
Read_Byte
00h
Reads 1 byte at starting address
Write_Byte
01h
Writes 1 byte at starting address
02h-FFh Reserved
TABLE 3. ASYNCHRONOUS SERIAL INTERFACE ERROR
CODES
COMMAND
NAME
CODE
(8 BITS)
DESCRIPTION
No Error
00h
No Error
Bus Error
01h
Bus Error
02h-FFh Reserved
TABLE 4. ASYNCHRONOUS SERIAL INTERFACE
READ_BYTE COMMAND FORMAT
DATA BYTE DESCRIPTION
(FIRST TO LAST)
LENGTH
(BYTES)
DIRECTION
Address (LSB)
1
In
Address (MSB)
1
In
Error
1
Out
Read data (0 bytes if error)
1
Out
TABLE 5. ASYNCHRONOUS SERIAL INTERFACE
WRITE_BYTE COMMAND FORMAT
DATA BYTE DESCRIPTION
(FIRST TO LAST)
LENGTH
(BYTES)
DIRECTION
Address (LSB)
1
In
Address (MSB)
1
In
Write data
1
In
Error
1
Out
ISL6590
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