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參數(shù)資料
| 型號： | ISL6580CR-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Integrated Power Stage |
| 中文描述： | 35 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC56 |
| 封裝： | 8 X 8 MM, PLASTIC, QFN-56 |
| 文件頁數(shù)： | 12/31頁 |
| 文件大小： | 1391K |
| 代理商： | ISL6580CR-T |
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12
V
VID
is the maximum output voltage at 0 load. It is set by a 5
or 6 bit binary input to the voltage regulator called VID
(Voltage ID). For VRD10, VID = 100011 indicates V
OUT
max
= 1.000V. The slope of the load line is different for other
applications. For VRM 9, Vout_max = V
VID
– Iload*.00095.
The slope and offset from V
VID
is adjustable in the ISL6580 /
ISL6590 using the user interface software. See the User
Interface Software section.
The ISL6580 / ISL6590 realize this behavior in a
programmable, lossless way. Load current is measured in
each ISL6580 output stage. A fraction (1/9900) of the current
in the upper MOSFET is mirrored and sent through an
external resistor. The voltage on the current sense resistor is
sampled near the end of the upper FET's ON time,
converted to a digital number and sent to the ISL6590
controller on the IDIGn line (see Figure 5). Current sensing
is described in more detail in the next section.
The sum of all power device currents is multiplied by a gain
factor, passed through a digital low pass filter and added to
the error voltage (see Figure 6).
The gain factor controls how much the output voltage
'droops' and is set by the system designer using the user
interface software. The user interface software calculates a
number of internal register values based on data in the
Large Signal Design, Inputs window. All values on the Inputs
window must be entered correctly for the AVP loadline to be
programmed correctly to the controller.
The user interface software will generate a plot of the
loadline. It is viewed by clicking on the AVP line button at the
bottom of all of the user interface software windows.
AVP offset moves the load line relative to the voltage
required by the input VID. It can be adjusted from 0 to 50mV
in steps of 3.125mV. AVP LoadLine controls the slope of the
load line. This gives the designer complete flexibility within
the specified "max" and "min" limits.
Current Sensing
Current sensing is a key feature in the Intersil Digital
Architecture. Precision current sensing is required to
maintain accurate load lines, good current sense balancing
between phases, thermal balancing, overload current, and
peak current limit protection.
By integrating the high side MOSFET in the power stage of
the Intersil Digital Architecture (see Figure 8), very accurate
current sensing can be achieved across temperature. This
method of current sense through integration is called current
mirroring. A current mirror simply designates a certain ratio
of transistors on the silicon of FET to have a separate source
output but a common drain node. As a result, a small current
sample from the FET can be drawn external to the power
stage and through a sense resistor. Voltage across the
sense resistor represents the total current through the High
Side FET. Since the mirror is using the same silicon as the
main current path, variations in Rdson and switching
characteristics mirror that of the main FET channel. The
internal structure of the sampling circuitry is seen in Figure 8.
FIGURE 5. CURRENT SENSE BLOCK DIAGRAM
FIGURE 6. AVP LOAD LINE CONTROL IS ADDED TO THE
ERROR SIGNAL
FIGURE 7. USER INTERFACE LOAD LINE ADJUSTMENTS
ISL6580
.
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