參數(shù)資料
型號： ISL658090EVAL2
廠商： Intersil Corporation
英文描述： Integrated Power Stage
中文描述： 集成功率級
文件頁數(shù)： 13/31頁
文件大小： 1391K
代理商： ISL658090EVAL2
13
A sample of the peak current through the MOSFET is taken
each clock cycle, converted to a digital signal, and sent to
the controller. The master oscillator frequency inside the
Intersil Digital Architecture is 133.33MHz. Figure 9 shows
the voltage drop across the sense resistor, the voltage at the
switch node, the inductor current, and the digital voltage
signal. The inductor current signal is delayed slightly due to
the probe parasitics. As can be seen from the figure, 13nS
prior to the turn off of the high side MOSFET a sample of the
voltage across the sense resistor is taken (I
SENSE
). This is
done to avoid voltage spiking during the switching of the
node. After sampling, I
SENSE
is converted to a digital signal
(I
DIG
). The controller receives the digital signal from the I
DIG
pin.
Current Sharing
Each ISL6580 senses current in it’s upper MOSFET as
described above and converts it to a serial digital signal on
the IDIGn lines. The sampled, digitized current, IDIG
n
, from
each active channel is used to gauge both overall load
current and the relative channel current carried in each leg of
the converter. The individual sample currents are summed
and divided by the number of active channels. The resulting
average current, I
AVG
, provides a measure of the total load
current demand on the converter and the appropriate level of
channel current. The average current is then subtracted from
the individual channel sample currents. The resulting error
current, I
ER
, is then filtered before it adjusts V
COMP
. The
modified V
COMP
signal is compared to a sawtooth ramp
signal and produces a pulse width which corrects for any
unbalance and drives the error current toward zero.
Loop Compensation
Any closed loop system must be designed to insure stability
(prevent oscillation) and provide correct response to external
events such as load transients. The output of a buck
regulator has an inherent, low pass filter formed by the
output inductor(s), output capacitance and their ESRs
(Equivalent Series Resistance). Figure 1 shows a typical
gain and phase plot of output inductors, capacitors and ESR.
FIGURE 8. INTERNAL STRUCTURE OF THE ISL6580 POWER
STAGE
FIGURE 9. VOLTAGE DROP ACROSS THE SENSE
RESISTOR, VOLTAGE AT SWITCH NODE,
INDUCTOR CURRENT, AND DIGITAL VOLTAGE
SIGNAL
Σ
+
IDIG1
IDIGn
+
+
Kav
-
CURRENT BALANCE
Σ
z
-1
++
Kiav
Σ
++
PWM n
GENERATE
BLOCK
Σ
FIGURE 10. CURRENT BALANCE
FIGURE 11. FREQUENCY RESPONSE OF THE OUTPUT
INDUCTORS AND CAPACITORS
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1
10
100
1000
10000
Frequency (in KHz)
P
-140
-120
-100
-80
-60
-40
-20
0
P
Plant Gain
Phase
ISL6580
相關PDF資料
PDF描述
ISL658090EVAL3 Integrated Power Stage
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