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參數(shù)資料
| 型號： | ISL6569ACB-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Multi-Phase PWM Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | PLASTIC, MS-013-AE, SOIC-24 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ISL6569ACB-T |
13
FN9092.2
December 29, 2004
Operation Initialization
Before converter operation is initialized, proper conditions
must exist on the enable and disable inputs. Once these
conditions are met, the controller begins a soft-start interval.
Once the output voltage is within the proper window of
operation, the PGOOD output changes state to update an
external system monitor.
Enable and Disable
The PWM outputs are held in a high-impedance state to
assure the drivers remain off while in shutdown mode. Four
separate input conditions must be met before the ISL6569A
is released from shutdown mode.
First, the bias voltage applied at VCC must reach the internal
power-on reset (POR) circuit rising threshold. Once this
threshold is met, the EN input signal becomes the gate for
soft-start initialization. Hysteresis between the rising and
falling thresholds insures that once enabled, the ISL6569A
will not inadvertently turn off unless the bias voltage drops
substantially. See
Electrical Specifications
for specifics on
POR rising and falling thresholds.
Second, the ISL6569A features an enable input (EN) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6569A in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of hysteresis
to prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6569A becomes enabled. The
schematic in Figure 8 demonstrates sequencing the
ISL6569A with the HIP660X family of Intersil MOSFET
drivers which require 12V bias.
Third, the frequency select/disable input (FS/DIS) will
shutdown the converter when pulled to ground. Under this
condition, the internal oscillator is disabled. The oscillator
resumes operation upon release of FS/DIS and a soft-start
sequence is initiated.
Finally, the 11111 VID code is reserved as a signal to the
controller that no load is present. The controller will enter
shutdown mode after receiving this code and will start up
upon receiving any other code.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.23V;
FS/DIS must not be grounded; and VID cannot be equal to
11111. Once these conditions are true, the controller
immediately initiates a soft-start sequence.
Soft-Start
The soft-start time, t
SS
, is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz per phase has a
soft-start time of
During the soft-start interval, the soft-start voltage, V
RAM
P
,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I
RAMP
, is
decreasing from 160
μ
A down to zero. These signals are
connected as shown in Figure 9 (I
OUT
may or may not be
connected to FB depending on the particular application).
The ideal diodes in Figure 9 assure that the controller tries to
regulate its output to the lower of either the reference voltage
or V
RAM
P
. Since I
RAMP
creates an initial offset across R
FB
(R
FB
x 160
μ
A), the first PWM pulse will not be seen until
V
RAMP
is greater than the R
F
B
I
RAMP
offset. This produces a
delay after the ISL6569A enables before the output voltage
starts moving. For example, if VID = 1.5V, R
FB
= 1k
and T
SS
= 8.3ms, the delay time can be expressed using Equation 10.
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
-
+
1.23V (± 2%)
EXTERNAL CIRCUIT
ISL6569A INTERNAL CIRCUIT
EN
+12V
VCC
+5V
POR
CIRCUIT
OV LATCH
SIGNAL
10.7k
1.40k
ENABLE
COMPARATOR
T
SS
SW
f
8.3ms
=
=
(EQ. 9)
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
-
+
I
AVG
REFERENCE
VOLTAGE
EXTERNAL CIRCUIT
ISL6569A INTERNAL CIRCUIT
COMP
C
C
R
C
R
FB
FB
IOUT
VDIFF
ERROR AMPLIFIER
V
COMP
V
RAMP
I
RAMP
IDEAL DIODES
t
DELAY
T
R
FB
160
1
10
6
–
×
--------1.4 VID
+
--------------------------------------------------
560
μ
s
=
=
(EQ. 10)
ISL6569A
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| ISL6569ACBZ | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6569ACBZ-T | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6569ACR | 功能描述:IC REG CTRLR BUCK PWM 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產(chǎn)品目錄頁面:1316 (CN2011-ZH PDF) |
| ISL6569ACR-T | 功能描述:IC REG CTRLR BUCK PWM 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產(chǎn)品目錄頁面:1316 (CN2011-ZH PDF) |
| ISL6569ACRZ | 功能描述:IC REG CTRLR BUCK PWM 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
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