參數(shù)資料
型號: ISL6567EVAL1
廠商: Intersil Corporation
英文描述: Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers
中文描述: 多用途兩相降壓PWM控制器集成MOSFET驅(qū)動器
文件頁數(shù): 22/26頁
文件大小: 659K
代理商: ISL6567EVAL1
22
Although the ISL6567 allows for external adjustment of the
channel-to-channel current balancing (via the R
ISEN
resistors), it is desirable to have a symmetrical layout,
preferably with the controller equidistantly located from the
two power trains it controls. Equally important are the gate
drive lines (UGATE, LGATE, PHASE): since they drive the
power train MOSFETs using short, high current pulses, it is
important to size them accordingly and reduce their overall
impedance. Equidistant placement of the controller to the
two power trains also helps keeping these traces equally
long (equal impedances, resulting in similar driving of both
sets of MOSFETs).
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C
IN
,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate all the high-frequency decoupling capacitors
(ceramic) as close as practicable to their decoupling target,
making use of the shortest connection paths to any internal
planes, such as vias to GND immediately next, or even onto
the capacitor’s grounded solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC. Locate the bypass capacitors, C
BP
,
close to the device. It is especially important to locate the
components associated with the feedback circuit close to
their respective controller pins, since they belong to a high-
impedance circuit loop, sensitive to EMI pick-up. It is
important to place the R
ISEN
resistors close to the
respective terminals of the ISL6567.
A multi-layer printed circuit board is recommended. Figure 26
shows the connections of the critical components for one
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
KEY
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
FIGURE 26. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
ISL6567
+12V
IN
Q1
Q2
Q3
Q4
COMP
FB
GND
VCC
BOOT1
BOOT2
UGATE1
UGATE2
REFTRK
LGATE1
LGATE2
L
IN
L
OUT1
(C
HFIN1
)
C
BIN1
(C
HFIN2
)
C
BIN2
C
BOOT1
C
BOOT2
L
OUT2
(C
HFOUT
)
C
BOUT
R
PG
R
2
R
1
C
1
C
2
(C
F1
)
PHASE1
PHASE2
V
OUT
PGND
PVCC
(C
F2
)
+5V
IN
MON
EN
R
FS
PGOOD
R
EN
HEAVY TRACE ON CIRCUIT PLANE LAYER
LOCATE NEAR SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
R
ISEN1
ISEN1
R
ISEN2
ISEN2
RGND
VSEN
VDIFF
C
SS
SS
FS
R
S
R
P
ISL6567
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