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參數(shù)資料
| 型號(hào)： | ISL6566IRZA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Three-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220VJJD-2, QFN-40 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 799K |
| 代理商： | ISL6566IRZA-T |
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20
FN9178.3
July 25, 2005
UPPER MOSFET POWER CALCULATION
In addition to r
DS(ON)
losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V
IN
) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-
recovery charge, Q
rr
, and the upper MOSFET r
DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 17,
the required time for this commutation is t
1
and the
approximated associated power loss is P
UP,1
.
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
2
. In Equation 18, the
approximate power loss is P
UP,2
.
A third component involves the lower MOSFET reverse-
recovery charge, Q
rr
. Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET body diode can recover all of Q
rr
, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P
UP,3
.
Finally, the resistive part of the upper MOSFET is given in
Equation 20 as P
UP,4
.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 17, 18, 19 and 20. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W
at
room temperature. See
Layout Considerations
paragraph for
thermal transfer improvement suggestions.
When designing the ISL6566 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P
Qg_TOT
, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 21
and 22, respectively.
In Equations 21 and 22, P
Qg_Q1
is the total upper gate drive
power loss and P
Qg_Q2
is the total lower gate drive power
loss; the gate charge (Q
G1
and Q
G2
) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
Q
is the driver total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are the number of upper and lower MOSFETs per
phase, respectively; N
PHASE
is the number of active
phases. The I
Q*
VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW
at
300kHz.
P
UP 1
V
IN
I
M
N
-----
I
2
--------
+
t
1
2
----
f
S
≈
(EQ. 17)
P
UP 2
,
,
V
IN
N
-----
---2
--------
–
2
----
≈
(EQ. 18)
I
M
I
t
2
f
S
P
UP 3
V
IN
Q
rr
f
S
=
(EQ. 19)
P
UP 4
r
DS ON
)
I
M
N
-----
2
d
I
2
--12
+
≈
(EQ. 20)
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
Q
VCC
+
+
=
(EQ. 21)
P
Qg_Q1
3
2
--
Q
G1
PVCC
F
SW
N
Q1
N
PHASE
=
P
Qg_Q2
Q
G2
PVCC
F
SW
N
Q2
N
PHASE
=
I
DR
3
2
--
Q
G1
N
Q1
Q
G2
N
Q2
+
N
PHASE
F
SW
I
Q
(EQ. 22)
+
=
Q1
D
S
G
R
GI1
R
G1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
PVCC
UGATE
ISL6566
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