參數(shù)資料
型號: ISL6564ACRZ
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Multiphase PWM Controller with Linear 6-Bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing
中文描述: SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PQCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-40
文件頁數(shù): 19/28頁
文件大?。?/td> 636K
代理商: ISL6564ACRZ
19
FN6285.1
March 20, 2007
Undervoltage Detection
The undervoltage threshold is set at 75% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, PGOOD gets pulled low.
Overvoltage Protection
When VCC is above 1.4V, but otherwise not valid as defined
under
Power-on Reset
in
Electrical Specifications
, the
overvoltage trip circuit is active using auxiliary circuitry. In
this state, an overvoltage trip occurs if the voltage at VSEN
exceeds 1.8V.
With valid VCC, the overvoltage circuit is sensitive to the
voltage at VDIFF. In this state, the trip level is 1.7V prior to
valid enable conditions being met as described in
Enable
and Disable
. The only exception to this is when the IC has
been disabled by an overvoltage trip. In that case the
overvoltage trip point is VID plus 200mV. During soft-start,
the overvoltage trip level is the higher of 1.5V or VID plus
200mV. Upon successful soft-start, the overvoltage trip level
is 200mV above VID. Two actions are taken by the
ISL6564A to protect the microprocessor load when an
overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns) until the
voltage at VSEN falls below 0.6V with valid VCC or 1.5V
otherwise. This causes the Intersil drivers to turn on the
lower MOSFETs and pull the output voltage below a level
that might cause damage to the load. The PWM outputs
remain low until VDIFF falls to the programmed DAC level
when they enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both
upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6564A will again command the lower
MOSFETs to turn on. The ISL6564A will continue to protect
the load in this fashion as long as the overvoltage condition
recurs.
Simultaneous to the protective action of the PWM outputs,
the OVP pin pulls to VCC delivering up to 100mA to the gate
of a crowbar MOSFET or SCR placed either on the input rail
or the output rail. Turning on the MOSFET or SCR collapses
the power rail and causes a fuse placed further up stream to
blow. The fuse must be sized such that the MOSFET or SCR
will not overheat before the fuse blows. The OVP pin is
tolerant to 12V (see
Absolute Maximum Ratings
), so an
external resistor pull-up can be used to augment the driving
capability. If using a pull-up resistor in conjunction with the
internal overvoltage protection function, care must be taken
to avoid nuisance trips that could occur when VCC is below
2V. In that case, the controller is incapable of holding OVP
low.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6564A is reset. Cycling the
voltage on EN or ENLL or VCC below the POR-falling
threshold will reset the controller. Cycling the VID codes will
not reset the controller.
Overcurrent Protection
ISL6564A has two levels of overcurrent protection. Each
phase is protected from a sustained overcurrent condition on
a delayed basis, while the combined phase currents are
protected on an instantaneous basis.
In instantaneous protection mode, the ISL6564A takes
advantage of the proportionality between the load current
and the average current, I
AVG
, to detect an overcurrent
condition. See the
Channel-Current Balance
section for
more detail on how the average current is measured. The
average current is continually compared with a constant
110
μ
A reference current as shown in Figure
12. Once the
average current exceeds the reference current, a
comparator triggers the converter to shutdown.
In individual overcurrent protection mode, the ISL6564A
continuously compares the current of each channel with the
same 110
μ
A reference current. If any channel current
exceeds the reference current continuously for eight
consecutive cycles, the comparator triggers the converter to
shutdown.
FIGURE 12. POWER GOOD AND PROTECTION CIRCUITRY
OVP
-
+
VID + 0.2V
VDIFF
-
+
110μA
I
AVG
-
+
DAC
REFERENCE
OV
OC
UV
PGOOD
75%
SOFT-START, FAULT
AND CONTROL LOGIC
-
+
OC
I
1
REPEAT FOR
EACH CHANNEL
110μA
ISL6564A
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