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參數(shù)資料
| 型號(hào)： | ISL6549IBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 420K |
| 代理商： | ISL6549IBZ |
15
FN9168.2
September 22, 2006
than the V
IN2
voltage. The FET’s gate-source rating should be
greater than 12V (even though the output voltage may not
require such a high gate voltage, load transients or other
disturbances might force LDO_DR to momentarily approach
12V). The FET threshold is not critical, except for the cases
where the LDO_DR headroom is diminished. And finally, the
package (and board area allowed) must be able to handle the
maximum power dissipation expected.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently at 600kHz,
the resulting current transitions from one device to another
cause voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and
printed circuit board design minimizes the voltage spikes in
the converters.
As an example, consider the turn-off transition of the PWM
upper MOSFET. Prior to turn-off, the MOSFET is carrying the
full load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the lower MOSFET and
parasitic diode. Any parasitic inductance in the switched
current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout of
the critical components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter
using the ISL6549. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multilayer printed circuit board is recommended. Figure 13
shows the connections of the critical components in the
converter. Capacitors C
IN
and C
OUT
could each represent
numerous physical capacitors. Dedicate one solid layer,
usually a middle layer of the PC board, for a ground plane and
make all critical component ground connections through vias
to this layer. Dedicate another solid layer as a power plane
and break this plane into smaller islands of common voltage
levels. Keep the metal runs from the PHASE terminal to the
output inductor short. The power plane should support the
input and output power nodes. Use copper filled polygons on
the top and bottom circuit layers for the phase node. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the LGATE and UGATE pins to the
MOSFET gates should be kept short and wide enough to
easily handle the several Amps of drive current.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitors, C
4
, C
5
, and C
6
close to their pins with a local GND connection, or via directly
to the ground plane. R12 should be placed near VCC5 and
PVCC5 pins. FS_DIS resistor R7 should be near the FS-DIS
pin, and its GND return should be short, and kept away from
the noisy FET GND. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors for both regulators should also be located as close
as possible to the relevant FB pin with vias tied straight to the
ground plane as required.
Then the switching components should be placed close to the
ISL6549. Minimize the length of the connections between the
input capacitors, C
IN
, and the power switches by placing them
nearby. Position both the ceramic and bulk input capacitors as
close to the upper MOSFET drain as possible, and make the
GND returns (from lower FET source to VIN cap GND) short.
Position the output inductor and output capacitors between
the upper MOSFET and lower MOSFET and the load.
References
Applications Note: AN1201
Visit us on the internet: www.intersil.com
FIGURE 13. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
V
OUT1
VCC5
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT
C
OUT1
C
IN1
V
IN1
KEY
COMP
ISL6549
UGATE
R
4
R
2
C
5
FB
LDO_DR
GND
VCC5
R1
V
OUT2
LDO_FB
C
2
VIA CONNECTION TO GROUND PLANE
C
OUT2
L
L
Q1
V
IN2
R5
R6
PHASE
R
3
C
3
C
1
Q2
VCC12
C
4
GND
VCC12
Q3
LGATE
C
IN2
PVCC5
C
6
PGND
PVCC5
R12
BOOT
C
7
FS_DIS
R
7
ISL6549
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