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參數(shù)資料
| 型號： | ISL6549CRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220VGGC, QFN-16 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 420K |
| 代理商： | ISL6549CRZ |
11
FN9168.2
September 22, 2006
Use the following guidelines for locating the poles and zeros of
the compensation network:
1. Select a value for R1 (1k
to 5k
, typically). Calculate
value for R2 for desired converter bandwidth (F
0
). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 10, the design procedure can
be followed as presented.
2. Calculate C1 such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
3. Calculate C2 such that F
P1
is placed at F
CE
.
4. Calculate R3 such that F
Z2
is placed at F
LC
. Calculate C3
such that F
P2
is placed below F
SW
(typically, 0.5 to 1.0
times F
SW
). F
SW
represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of F
P2
lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equation 8 describes the frequency
response of the modulator (G
MOD
), feedback compensation
(G
FB
) and closed-loop response (G
CL
):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the
log-log graph of Figure 11 by adding the modulator gain, G
MOD
(in dB), to the feedback compensation gain, G
FB
(in dB). This is
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C1
R2
R1
FB
C2
R3
C3
L
C
V
IN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
E
EXTERNAL CIRCUIT
ISL6549
V
OUT
V
OSC
D
UGATE
LGATE
Ro
PHASE
R2
V
R1 F
MAX
IN
LC
---------------------------------------------
=
(EQ. 4)
C1
2
π
R2 0.5 F
LC
-----------------------------------------------
=
(EQ. 5)
C2
CE
1
–
---------------------------------------------------------
=
(EQ. 6)
R3
LC
------------
1
–
---------------------
=
C3
SW
-------------------------------------------------
=
(EQ. 7)
G
MOD
f
( )
d
V
V
OSC
-----------------------------
1
s f
( )
E
D
+
(
)
C
s
2
f
( )
L C
+
+
-------------------------------+
=
G
FB
f
( )
+
C1
C2
(
)
--------+
=
)
C3
1
s f
( )
R3 C3
+
(
)
1
s f
( )
R2
C2
--------+
+
----------------------------------+
G
CL
f
( )
G
MOD
f
( )
G
FB
f
( )
=
where s f
( )
2
π
=
(EQ. 8)
F
Z1
-------------------------------
=
F
Z2
+
2
π
R1
R3
(
)
C3
---------------------------------------------------
=
F
P1
2
π
R2
C1
+
C2
----------------------
----------------------------------------------
=
F
P2
2
π
R3 C3
-------------------------------
=
(EQ. 9)
ISL6549
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