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參數(shù)資料
| 型號(hào)： | ISL6549CAZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, QSOP-16 |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 420K |
| 代理商： | ISL6549CAZ |
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9
FN9168.2
September 22, 2006
soft-start cycles (1 internal soft-start ramp cycle, plus
one-quarter on the next).
If either V
INx
voltage is not present at startup, that will cause a
UV shutdown and restart cycle; similarly, if either V
INx
is
removed after start-up, a shutdown and restart cycle will start
when its output drifts down to the UV trip point. But in both
cases, once the V
INx
is restored, the V
OUTs
will recover on
the next soft-start ramp.
Figure 5 shows an example of the start-up, with V
IN1
not
powered. V
OUT2
ramps up one-quarter of the way, at which
time the UV comparators are enabled. Since V
IN1
is not
present, V
OUT1
will not be following the soft-start ramp up,
and it will fail the test for UV, shutting down both outputs. It
starts an internal delay time-out (equal to one soft-start
interval), and then starts a new ramp. For this example, it
shows about a 1.6ms ramp up, and 6.4ms off, before the next
ramp starts. Thus, the total period of 8ms is based on 1.25
soft-start cycles (one-quarter of the first ramp, and then one
full time-out, at a clock period of around 1.6μs) The dotted
magenta line shows the case where V
OUT2
is allowed to
ramp all of the way up to 2V.
Switching Frequency
The switching frequency of the ISL6549 is determined by the
value of the FS resistor. The graph in Figure 6 shows the
dependence between the resistor chosen and the resulting
switching frequency.
Output Voltage Selection
The output voltage of the PWM converter can be programmed
to any level between V
IN1
and the internal reference, 0.8V.
However, even though the ISL6549 can run at near 100%
duty cycle at zero load, additional voltage margin is required
above V
IN1
to allow for loading. An external resistor divider is
used to scale the output voltage relative to the reference
voltage and feed it back to the inverting input of the error
amplifier (see Figure 7). A typical value for R1 may be 1.00k
(±1% for accuracy), and then R4 (also ±1%) is chosen
according to Equation 1:
R1 is also part of the compensation circuit (see
“PWM
Controller Feedback Compensation” on page 10
for more
details), so once chosen for that, it should not be changed to
adjust V
OUT1
; only change R4. If the output voltage desired
is 0.8V, simply route V
OUT1
back to the FB pin through R1,
but do not populate R4. V
OUT1
voltages less than the 0.8V
reference are not available.
The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 8. Select a
value for R5 (typical 1.00k
±1% for accuracy), and use
Equation 2 to calculate R6 (also ±1%), where V
OUT2
is the
desired linear regulator output voltage and V
REF
is the
internal reference voltage, 0.8V. For an output voltage of
0.8V, simply populate R5 with a value less than 5k
and do
not populate R6. V
OUT2
voltages less than the 0.8V
reference are not available.
FIGURE 5. UNDERVOLTAGE PROTECTION (SIMULATED BY
HAVING NO VIN1 ON POWER-UP)
GND>
V
OUT2
(0.5V/DIV)
V
OUT2
(0.5V/DIV)
1.6ms
6.4ms
V
OUT1
(0.5V/DIV)
100k
1M
10k
100k
R (k
)
1M
F
FIGURE 6. FREQUENCY vs FS RESISTOR
R4
0.8V
–
×
VOUT1
0.8V
-----R1
=
(EQ. 1)
FIGURE 7. OUTPUT VOLTAGE SELECTION OF THE
SWITCHER (V
OUT1
)
R1
C3
C
OUT1
V
OUT1
R4
L
OUT
ISL6549
Q1
FB
UGATE
COMP
R2
C1
C2
R3
Q2
LGATE
V
IN1
+
C
IN1
+
VOUT
1
0.8
1
1
R
4
R
+
×
=
PHASE
R
6
5
0.8V
0.8V
–
×
VOUT
2
-----R
=
(EQ. 2)
ISL6549
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