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參數(shù)資料
| 型號： | ISL6535CBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous Buck Pulse-Width Modulator (PWM) Controller |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 397K |
| 代理商： | ISL6535CBZ |
9
FN9255.0
January 17, 2006
circuit traces for the MOSFETs’ gate and source connections
from the ISL6535 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin
and locate the capacitor, C
ss
close to the SS pin as the
internal current source is only 30
μ
A. Provide local V
CC
decoupling between VCC and GND pins. Locate the
capacitor, C
BOOT
as close as practical to the BOOT pin and
the phase node.
Compensating the Converter
The ISL6535 Single-phase converter is a voltage-mode
controller. This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 6).
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V
IN
at the PHASE node. The PWM wave is smoothed by the
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a
DC gain and shaped by the output filter, with a double pole
break frequency at F
LC
and a zero at F
CE
. For the purpose
of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6535) and the external R
1
-R
3
, C
1
-C
3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
0
; typically 0.1 to 0.3 of F
SW
) and adequate
phase margin (better than 45 degrees). Phase margin is the
difference between the closed loop phase at F
0dB
and 180°.
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
1
, R
2
, R
3
, C
1
, C
2
,
and C
3
) in Figures 6 and 7. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R
1
(1k
to 10k
, typically). Calculate
value for R
2
for desired converter bandwidth (F
0
). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented. As the ISL6535 supports 100%
duty cycle, D
MAX
equals 1. The ISL6535 uses a fixed
ramp amplitude (V
OSC
) of 1.9V, the above equation
simplifies to:
FIGURE 6. COMPENSATION CONFIGURATION FOR THE
ISL6535 CIRCUIT
ISL6535
COMP
C
1
R
2
R
1
FB
VOUT
C
2
R
3
C
3
F
LC
2
π
L C
---------------------------
=
F
CE
---------------------------------
=
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C
1
R
2
R
1
FB
C
2
R
3
C
3
L
C
V
IN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
ESR
EXTERNAL CIRCUIT
ISL6535
V
OUT
V
OSC
DCR
UGATE
PHASE
LGATE
GND
R
2
V
R
F
MAX
IN
LC
----------------------------------------------
=
R
2
1.9 R
F
0
IN
LC
-------------------------------
=
ISL6535
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