參數(shù)資料
型號: ISL6525CB
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller
中文描述: SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO14
封裝: PLASTIC, MS-012-AB, SOIC-14
文件頁數(shù): 6/11頁
文件大?。?/td> 120K
代理商: ISL6525CB
6
2. The minimum I
OCSET
from the specification table.
3. Determine
where
I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
,
A small ceramic capacitor should be placed in parallel with
R
OCSET
to smooth the voltage across R
OCSET
in the
presence of switching noise on the input voltage.
Programming PGOOD Delay Time
The PGOOD rising edge delay can be programmed by
connecting a small capacitor C
DELAY
between the DELAY pin
and GND. The rising-edge delay is determined by the 10
μ
A
discharging current source I
DISCH
, the voltage difference
between VCC and the gate threshold voltage V
TH
of the open-
drain FET, and the capacitor value. The delay time t
DELAY
can
be calculated with the following equation,
V
TH
is typically 2V, VCC is 12V, and I
DISCH
is 10
μ
A. Thus,
1nF of C
DELAY
leads to 1ms of delay time typically.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
Please note that the capacitors C
IN
and C
O
each represent
numerous physical capacitors. Locate the ISL6525 within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the ISL6525
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
ss
close to the SS pin because the internal current source is
only 10
μ
A. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
PEAK
for I
PEAK
I
OUT MAX
)
I
(
)
2
+
>
t
DELAY
C
VCC
-----------------------------------------------------------
V
(
)
DISCH
=
PGND
L
O
C
O
LGATE
UGATE
PHASE
Q1
Q2
D2
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
V
IN
V
OUT
RETURN
ISL6525
C
IN
L
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+12V
ISL6525
SS
GND
VCC
BOOT
D1
L
O
C
O
V
OUT
L
Q1
Q2
PHASE
+V
IN
C
BOOT
C
VCC
C
SS
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
-
+
REF
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6525
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
Z
FB
ISL6525
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